Senior FPGA Design Engineer

UST; Bengaluru Urban; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

UST in Bengaluru is seeking a Senior FPGA Design Engineer to port, adapt, and optimize complex IP cores for FPGA targets. The role includes migrating ASIC RTL and system models into robust FPGA architectures, and managing high-speed protocol integration and timing closure.

You will evaluate IP compatibility and rewrite RTL wrappers to fit FPGA fabrics, ensuring the final system meets strict performance and timing requirements.

Qualifications

• Bachelor's or Master's Degree in Electronics Engineering or similar.
• 8+ years of hands-on digital design and FPGA implementation experience (Senior Level).
• Languages: Strong proficiency in HDL like Verilog, SystemVerilog or VHDL.
• Vendor Toolchains: Experience with Xilinx Vivado, Altera Quartus.
• Simulation & Verification: Proficiency with ModelSim, VDS or UVM/self-checking test benches.
• Timing & Closure: Deep understanding of STA, CDC techniques and timing constraints.

Responsibilities

• Migrate ASIC RTL, System level models or third-party IP into FPGA architectures.
• Manage high-speed protocol integration and advanced timing closure.
• Evaluate IP compatibility, rewrite/wrapper-engineer RTL for FPGA fabrics.
• Ensure final system meets strict performance and timing requirements.

Skills

Verilog/SystemVerilog/VHDL

FPGA design

STA

UVM

Education

Bachelor's or Master's Degree in Electronics Engineering

Tools

Xilinx Vivado

Altera Quartus

ModelSim

VDS

UVM

Job description

• We are seeking a Senior FPGA Design Engineer specializing in porting, adapting, and optimizing complex IP cores to FPGA targets. In this role, the engineer will be responsible for the migration of ASIC RTL, System level models, or third-party IP into robust FPGA architectures, specifically managing high-speed protocol integration and advanced timing closure. The engineer will also be responsible for evaluating IP compatibility, rewriting or wrapper-engineering RTL to fit target FPGA fabrics, and ensuring the final system meets strict performance and timing requirements.

Job Requirement:

• Bachelor's or Master's Degree in Electronics Engineering or similar
• 8+ years of hands-on digital design and FPGA implementation experience (Senior Level)
• Languages: Strong proficiency in hardware description languages like Verilog, SystemVerilog or VHDL
• Vendor Toolchains: Experience with major design suites such as Xilinx Vivado, Altera Quartus etc.
• Simulation & Verification: Proficiency with tools like ModelSim, VDS or functional verification methodologies (UVM/Self-checking test benches)
• Timing & Closure: Deep understanding of static timing analysis (STA), Clock domain crossing (CDC) techniques and creating timing constraints.
• Interfaces and Protocols: Familiarity with high-speed serial and parallel protocols like PCIe, USB (10G/10G), DDR4/DDR5 memory, I2C and SPI.