Role Overview
We are seeking an experienced FPGA Design Engineer with 5 to 10 years of hands‑on expertise in FPGA development, design flow, and hardware debugging. The ideal candidate will have strong knowledge of FPGA tools, RTL design, and protocols, with exposure to domain‑specific applications such as SDI, DisplayPort, HDMI, and Ethernet.
Key Responsibilities
- Design, implement, and verify FPGA‑based solutions across multiple domains.
- Work with FPGA design flow including synthesis, place‑and‑route (PNR), and timing closure.
- Perform timing analysis and resolve timing‑related issues.
- Conduct simulation using Questasim and validate designs.
- Debug hardware in lab setups using oscilloscopes, analyzers, and FPGA debuggers.
- Enhance and maintain design documentation based on project updates and improvements.
- Collaborate with cross‑functional teams to integrate FPGA designs into larger systems.
Required Skills & Experience
- Strong knowledge of FPGAs and hands‑on experience with synthesis and implementation tools, such as Libero, Vivado, or Quartus.
- Proficiency in RTL design (Verilog/VHDL).
- Experience with FPGA hardware platforms and lab‑based validation.
- Hands‑on experience with Tcl scripting for automation.
- Understanding of IPs such as transceivers, DDR, and PCIe.
- Familiarity with simulation tools like Questasim.
- Strong debugging skills using hardware tools (oscilloscopes, analyzers, etc.).
Domain Knowledge (Preferred)
- SDI, DisplayPort, HDMI 2.2, SLVS
- Motor Control, Holoscan
- TSN (Time‑Sensitive Networking), Ethernet protocols
Desired Attributes
- Strong problem‑solving and analytical skills.
- Ability to work independently and in collaborative team environments.
- Excellent documentation and communication skills.
- Passion for exploring new FPGA trends and applying them to real‑world applications.
- FPGA design and validation experience.
- Experience validating FPGA designs on board.
- Proficient with scripting language like Tcl.
- Good understanding of lint and CDC.
- Knowledge of usage of AI agents and prompt engineering is a plus.