FPGA Design Engineer

UST; Bengaluru Urban; Sur place; INR 3 500 000 - 6 000 000; Plein temps

Résumé du poste

UST seeks a Senior FPGA Design Engineer to port, adapt, and optimize complex IP cores for FPGA targets. The role involves migrating ASIC RTL, System models, or third-party IP into FPGA architectures, with emphasis on high-speed protocol integration and timing closure.

Candidate should have hands-on FPGA experience, 8+ years in digital design, and strong Xilinx toolchain proficiency. Bengaluru-based on-site position with opportunities to work on PCIe/USB, DDR4/DDR5 interfaces.

Qualifications

• 8+ years of hands-on digital design and FPGA implementation experience.
• Experience porting and adapting complex IP cores to FPGA targets.
• Proven ability to migrate ASIC RTL/system models to FPGA architectures with timing closure.

Responsabilités

• Translate system requirements into synthesizable RTL architectures.
• Optimize designs for clock frequency and resource usage while meeting timing.
• Analyze and wrap/port IP cores for Xilinx UltraScale platforms and high-speed interfaces.

Connaissances

Verilog

SystemVerilog

VHDL

UVM

Formation

Bachelor's or Master's in Electronics Engineering

Outils

Xilinx Vivado

Altera Quartus

ModelSim

VDS

Description du poste

We are seeking a Senior FPGA Design Engineer specializing in porting, adapting, and optimizing complex IP cores to FPGA targets. In this role, the engineer will be responsible for the migration of ASIC RTL, System level models, or third-party IP into robust FPGA architectures, specifically managing high-speed protocol integration and advanced timing closure. The engineer will also be responsible for evaluating IP compatibility, rewriting or wrapper-engineering RTL to fit target FPGA fabrics, and ensuring the final system meets strict performance and timing requirements.

Position Type & Location

Education & Experience Requirements

• Education: Bachelor's or Master’s Degree in Electronics Engineering or similar
• Work Experience: 8+ years of hands-on digital design and FPGA implementation experience (Senior Level)
• Project History: A track record of successfully porting, adapting, and validating complex IP cores on high-speed FPGA platforms

Core Technical Skills

• Languages: Strong proficiency in hardware description languages like Verilog, SystemVerilog or VHDL
• Vendor Toolchains: Experience with major design suites such as Xilinx Vivado, Altera Quartus etc.
• Simulation & Verification: Proficiency with tools like ModelSim, VDS or functional verification methodologies (UVM/Self-checking test benches)
• Timing & Closure: Deep understanding of static timing analysis (STA), Clock domain crossing (CDC) techniques and creating timing constraints.
• Interfaces and Protocols: Familiarity with high-speed serial and parallel protocols like PCIe, USB (10G/10G), DDR4/DDR5 memory, I2C and SPI.

Advanced Technical Requirements

• Xilinx/Vivado & UltraScale(+) Expertise: Expert in AMD/Xilinx Vivado (synthesis, implementation, bitstream) and deep knowledge of Virtex UltraScale/UltraScale+ primitives. Strong experience with IP Integrator and Xilinx IP configuration.
• IP Porting & Migration: Proven track record migrating ASIC RTL/3rd-party IP to FPGA-friendly architectures, replacing ASIC‑specific cells (clock gates, memories, PLLs, etc.) with Xilinx equivalents, and developing clean RTL wrappers/bridge logic.
• High-Speed Interfaces: Hands‑on integration of Xilinx GTH/GTY transceivers and high-speed protocols (USB 3.x/4, MIPI C‑PHY/D‑PHY, CSI/DSI).
• Timing Closure & Physical Optimization: Advanced STA skills, strong XDC constraint development (false/multicycle paths, clock groups), CDC/reset synchronization expertise, and experience with floor planning, physical optimization, and routing in dense UltraScale designs.

Key Responsibilities:

• RTL Design: Translate system requirements and algorithmic models into clean, synthesizable RTL architectures.
• Optimization: Optimize designs for clock frequency, power efficiency, and hardware resource
• Analyze, modify, and optimize incoming IP cores to align with Xilinx UltraScale hardware resources, power profiles, and speed grades.