FPGA Prototyping/Emulation Engineer

Ceremorphic, Inc.; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Ceremorphic, Inc. is seeking an FPGA design engineer to own the design, implementation, and verification of next‑generation FPGA prototypes for SOCs. You will drive FPGA timing closure, interface integration (PCIe, DDR, etc.), and provide an emulation platform for firmware development.

You will work with Verilog and SystemVerilog, partition large ASIC designs into FPGA subsystems, and debug using Chipscope and lab equipment. Collaboration with software for HW-SW co-debug is essential.

Qualifications

• Hands-on design using Verilog and SystemVerilog; porting large designs to FPGA with RTL and IP cores.
• Ability to partition a big ASIC design into multiple FPGA subsystems and interconnect them.
• Proficiency in Perl and Tcl language.
• Hardware debugging using FPGA tools (Chipscope) and lab equipment (oscilloscopes, logic analyzers).
• Hands-on experience with PCIe controller, DMA and knowledge of AXI protocols; ARM experience is preferred.
• Collaborate with software for HW-SW co-debug.

Responsibilities

• FPGA integration and implementation of all interfaces (PCIe, DDR, etc).
• FPGA implementation and timing closure
• Provide emulation platform solution for FW development
• Provide emulation platform for pre-silicon validation
• FPGA validation and debug

Skills

Verilog

SystemVerilog

PCIe

AXI

DMA

ARM

Perl

Tcl

Tools

Chipscope

Oscilloscopes

Logic Analyzers

PCIe controller

Job description

The candidate would own and drive the design, implementation, and verify FPGA prototypes of next-generation SOCs. The responsibilities mainly cover the following:

• FPGA integration and implementation of All interfaces (PCIe, DDR, etc)
• FPGA implementation and timing closure
• Provide emulation Platform solution for FW development
• Provide emulation Platform for Pre silicon Validation
• FPGA Validation and debug

Key Requirements

• Hands on design experience using Verilog, System Verilog and porting large designs to FPGA including combination of custom RTL as well as proven IP cores.
• Ability to partition a big AISC design into multiple FPGA sub-systems and implement modules for interconnection between these sub-systems.
• Proficiency in Perl, Tcl language.
• Good hardware debug skills using FPGA debug tools like Chipscope and lab debug equipment like Oscilloscopes and Logic Analyzers to root cause issues at silicon or board level.
• Hands on experience using PCIe controller, DMA and working knowledge of AXI protocols and ARM is required
• Ability to work closely with software team and get involved in hardware-software co-debug.