Principal Design Engineer - ( Synthesis/LEC/CLP )

Cadence; Bengaluru; On-site; INR 3,500,000 - 6,500,000; Full time

Job summary

Cadence in Bengaluru/Pune is seeking a Principal Design Engineer to drive Synthesis, LEC, CLP and UPF/CPF power‑intent verification. You will own flows, improve methodologies, and resolve root causes across synthesis and sign‑off for complex ASIC/SoC blocks.

The role requires leading cross‑team discussions, documenting status, and delivering robust low‑power solutions in a fast‑paced environment. BE/BTech/ME/MS/MTech in Electrical/Electronic is expected.

Qualifications

• 8–12 years of hands‑on ASIC/SoC design experience with strong depth in Synthesis (Genus), LEC (Conformal), and Low Power.
• Proven experience across multi‑corner, multi‑mode sign‑off considerations.
• Strong scripting ability in TCL, Python, PERL etc.
• Deep understanding of ASIC flow interactions: RTL, synthesis, physical design handoff, DFT.
• Excellent written and verbal communication skills; comfortable owning technical documentation and cross‑team discussions.

Responsibilities

• Drive methodology improvements and best‑practice development across Synthesis, LEC, CLP and ECO flows.
• Own end‑to‑end LEC sign‑off across multiple design blocks including debug of NEQs, aborts.
• Drive Physical synthesis closure on complex blocks including constraint development and PPA closure.
• CLP sign‑off for low‑power intent designs: level shifter, retention, isolation, PSO strategy architecture, supply set/domain conflict resolution.
• Own technical documentation, status tracking, and write‑ups across active blocks.

Skills

ASIC/SoC design

Synthesis

LEC

Low Power

Sign-off

TCL scripting

Python

Perl

RTL

DFT

Communication

Documentation

Education

BE/BTech/ME/MS/MTech in Electrical/Electronic

Tools

Genus

Conformal

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well‑being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Location: Pune/Bangalore

Experience: 8–12 Years

BE/BTech/ME/MS/MTech in Electrical/Electronic or equivalent

About The Role

We are looking for a Principal Design Engineer to drive Synthesis, Logical Equivalence Checking (LEC), Conformal Low Power (CLP), and UPF/CPF-based power intent verification. This is an internally facing role contributing to flow methodology & root‑cause resolution on synthesis, Logical Equivalence Checking (LEC), low‑power sign‑off.

Key Responsibilities

• Drive methodology improvements and best‑practice development across Synthesis, LEC, CLP and ECO flows.
• Own end‑to‑end LEC sign‑off across multiple design blocks including debug of NEQs, aborts.
• Drive Physical synthesis closure on complex blocks including constraint development and PPA closure.
• CLP sign‑off for low‑power intent designs: level shifter, retention, isolation, PSO strategy architecture, supply set/domain conflict resolution.
• Own technical documentation, status tracking, and write‑ups across active blocks.

Required Skills

• 8–12 years of hands‑on ASIC/SoC design experience with strong depth in Synthesis (Genus), LEC (Conformal), and Low Power.
• Proven experience across multi‑corner, multi‑mode sign‑off considerations
• Strong scripting ability in TCL, Python, PERL etc.
• Deep understanding of ASIC flow interactions: RTL, synthesis, physical design handoff, DFT.
• Excellent written and verbal communication skills; comfortable owning technical documentation and cross‑team discussions
• Proven track record and experience working in a fast‑paced environment.

Preferred

• Experience with physically aware synthesis flows

Regards

K Madhu Prasad

[e-mail]

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