Principal Design Engineer(RTL)

NXP Semiconductors NV; Pune District; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NXP Semiconductors NV in Pune, India is seeking a Digital Design Engineer to define and realize digital functions for IPs, subsystems or ICs based on specifications. You will engage in design, verification, and evaluation to meet quality and reliability needs, and you may contribute to problem solving within the digital and system domain.

The role covers IP delivery, silicon validation support, and potentially the full ASIC design cycle from RTL coding through backend support and silicon

Responsibilities

• The Digital Design Engineer is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications.
• He is responsible for design, verification and evaluation of those. He is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.
• The candidate will work as a design engineer for wireless/communication ASICs development.
• The main responsibilities include IP delivery and silicon validation support.
• The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.

Job description

• The Digital Design Engineer is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications.
• He is responsible for design, verification and evaluation of those. He is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.
• The candidate will work as a design engineer for wireless/communication ASICs development.
• The main responsibilities include IP delivery and silicon validation support.
• The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.