Principal Design Engineer

Cadence Design Systems, Inc.; Pune District; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Cadence Design Systems, Inc. in Pune, India is seeking a Performance Modeling Engineer to develop cycle-level performance models using SystemC/C++ and to support architectural tradeoffs for next‑generation memory controller architectures.

You will correlate models with RTL configurations, analyze throughput and latency, and work with memory architects to implement features. Proficiency in C++, SystemC/TLM, Verilog, UVM, and Python with data analysis tools is required.

Qualifications

• BE/B.Tech/ME/MTech in ECE, E&TC or CS or equivalent.
• 8+ years of hardware modeling, functional or performance experience.
• Strong coding skills in C++, SystemC and TLM.

Responsibilities

• Develop cycle-level performance models in SystemC or C++.
• Correlate models with RTL configurations and traffic.
• Collaborate with Memory Architects on feature requirements and implementations.
• Analyze architectural trade-offs for throughput and cost.
• Develop synthetic memory traffic and automate performance metrics.

Skills

C++

SystemC

TLM

Python

Verilog

SV

UVM

Pandas

Matplotlib

Education

BE/B.Tech in ECE/ETC/CS

ME/M.Tech

Tools

SystemC

RTL-Verilog

UVM

Simulators

Python

Pandas

Matplotlib

Job description

PUNE

Full time

R47483

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Performance Modeling Engineer

Location - India (Pune)

Summary

We are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.

Responsibilities

• Develop cycle-level performance models in SystemC or C++

• Correlate performance models to match RTL configurations and traffic conditions

• Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model

• Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices

• Develop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)

• Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Required Skills

• BE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar

• 8+ years of experience in hardware modeling, functional or performance

• Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)

• Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs

Additional Skills

• Understand RTL-Verilog, SV, UVM and experience analyzing waveforms

• Understand memory protocols and timing - DDR4, DDR5, LP4, LP5

• Experience using performance simulators - Memory Controller, NoC, CPU models

• Coding in Python and familiarity with packages like Pandas, Matplotlib

• Experience working with performance benchmarks - SPEC, STREAM, etc

• Concepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies

• We're doing work that matters. Help us solve what others can't.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.