Lead Design Engineer

Cadence Design Systems; Hyderabad; On-site; INR 1,800,000 - 3,000,000; Full time

Job summary

Cadence Design Systems in Hyderabad, India, invites a Lead Design Engineer for SoC/Subsystem/IP design with 4–18 years of experience to own RTL development from architecture to closure. You will drive high-quality, reusable designs in Verilog/SystemVerilog, partnering with verification, physical design, DFT, firmware, and architecture teams.

Responsibilities include translating requirements into micro-architecture, leading key blocks, and ensuring timing, power, and area targets while mentoring

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.
• 10 to 14 years of experience in digital design with exposure to IP, subsystem, and SoC development.
• Strong expertise in RTL design using Verilog/SystemVerilog.

Responsibilities

• Own end-to-end RTL design and development of SoC, subsystem, and IP blocks.
• Translate architecture and product requirements into micro-architecture and implementation plans.
• Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability.
• Lead design of interconnects, controllers, bridges, memory interfaces, datapaths, and control logic.
• Drive block- and subsystem-level design integration and resolve interface, timing, and functionality issues.
• Collaborate with verification, physical design, DFT, firmware, and architecture teams for robust design closure.

Skills

RTL design

Verilog/SystemVerilog

AMBA AXI/AHB/APB

Micro-architecture

Debugging

Scripting

Education

Bachelor’s or Master’s in Electronics / ECE / related

Tools

Python

Perl

Tcl

Shell

Job description

Job Profile

Job Profile Role Title Lead Design Engineer, SoC / Subsystem / IP Design Experience 4to 18 years Qualification:BE/BTECH/ME/MTECH

Role Summary

Lead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets.

Key Responsibilities

Own end-to-end RTL design and development of SoC, subsystem, and IP blocks. Translate architecture and product requirements into detailed micro-architecture and implementation plans. Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability. Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic. Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues. Work closely with verification teams to review test plans, support debug, and ensure design quality and closure. Collaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints. Support DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues. Review specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality. Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases. Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology. Contribute to design methodology improvements, reusable IP development, and automation initiatives.

Required Skills and Qualifications

Required Skills and Qualifications Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field. 10 to 14 years of experience in digital design with strong exposure to IP, subsystem, and SoC development. Strong expertise in RTL design using Verilog/SystemVerilog. Solid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design. Strong experience in micro-architecture definition and hardware implementation. Good understanding of AMBA protocols such as AXI, AHB, and APB. Experience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges. Strong debugging skills for simulation, synthesis, and integration issues. Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows. Exposure to power, performance, and area optimization techniques. Scripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements. Strong communication and cross-functional collaboration skills.

Preferred Skills

Preferred Skills Experience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs. Exposure to low-power design methodologies including UPF/CPF. Experience with formal verification support and silicon debug. Experience leading small design teams or owning major subsystems in large SoC programs.

Key Competencies

• RTL and micro-architecture ownership
• SoC and subsystem integration
• Technical leadership
• Problem solving and debug
• Quality and design closure focus

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Company Information

Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.