Mixed- Signal Systems and Verification Engineer

Cadence Design Systems; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Cadence Design Systems in Bengaluru is seeking an AMS Verification Engineer to develop and verify analog behavioral models for RF/analog blocks using SystemVerilog. You will integrate models with RTL and verify accuracy against analog schematics, using test benches, scenarios, and assertions, while leveraging DSP knowledge where possible.

Strong scripting skills are valued. The role emphasizes hands-on development within a team that upholds engineering excellence and innovation.

Qualifications

• Experience in developing and verifying real-numbered behavioral models in SystemVerilog.
• Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS.
• Working knowledge of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer.
• Experience with low-power architecture.
• Experience with Cadence Virtuoso Schematic Composer and ADE.
• Experience in Analog Assertion Based Verification.
• Experience in TB development is a plus.
• Experience in scripting with Perl or Python.
• Excellent communication skills.

Responsibilities

• Develop accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
• Verify models against analog schematics as representations of intended behavior.
• Integrate models with RTL.
• Verify analog functionalities against design specs using test benches, scenarios, and assertions.
• DSP experience is a huge plus.
• Document modeling and verification results for formal review.

Skills

SystemVerilog

Python scripting

Perl scripting

Analog/mixed-signal modeling

Communication

Tools

Cadence Virtuoso Schematic Composer

Cadence ADE

Verilog-AMS

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Qualifications

• New graduates strongly encouraged to apply!
• Experience in developing and verifying real-numbered behavioral models in SystemVerilog
• Understanding of SystemVerilog, RNM, UDN/UDT/UDR, wreal, and Verilog-AMS
• Basic understanding of AMS blocks like filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, Mixer, etc
• Working experience in low power Architecture
• Working experience in Cadence Virtuoso Schematic Composer and ADE
• Experience with Analog Assertion Based Verification
• Experience in TB development will be a strong plus
• Experience in writing scripts in languages such as Perl or Python
• Excellent teammate with excellent communication skills
• Experience with FPGA prototyping is a plus

Responsibilities

• You will become part of a hands-on development team that fosters engineering excellence, creativity, and innovation.
• As an AMS Verification Engineer, you will be responsible for Developing accurate and simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
• Verifying that the behavior models are accurate representations of analog schematics
• Integrating the models with RTL
• Verifying analog functionalities against design specifications using analog behavioral models: for example, coding test benches, test scenarios, and assertions.
• DSP experience a huge plus.
• Documenting modeling and verification results for formal review

We're doing work that matters. Help us solve what others can't

We're doing work that matters. Help us solve what others can't

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