Power-Domain Verification Lead

Axiado; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Axiado is seeking a Verification Lead for Power Aware Simulation to join our team working on Smart Edge SoCs for network, control, security, and IIoT applications.

You will drive UPF verification with UVM testbenches, develop RTL/SOC verification strategies, and collaborate with RTL and power architects while using scripting tools like Python and Make.

Qualifications

• 10+ years of hands-on SystemVerilog and UVM verification.
• Strong UPF/power intent modeling knowledge.
• Experience with power-aware simulation.
• Understanding of power domains, reset vs power interactions.
• Debug skills across RTL, UPF, and testbenches.
• BE/BTech or MTech in EE/EECS/CS or equivalent.

Responsibilities

• Execute power-aware simulations and debug power intent issues.
• Integrate UPF with UVM testbenches and VIPs.
• Verify RTL/SOC and gate-level simulations.
• Create directed and constrained-random tests for low-power scenarios.
• Develop assertions and coverage for power states and transitions.
• Collaborate with RTL and power architects.
• Support power-aware regression and sign-off.
• Use scripting languages (Make, Perl, Python, Shell).

Skills

SystemVerilog & UVM

UPF / power modeling

Power-aware simulation

RTL verification

Scripting: Make, Python, Perl

Education

BE/BTech or MTech in EE/EECS/CS

Job description

Job Description

Verification Lead Power Aware Simulation position is your opportunity to join a leading company in Smart Edge SoCs for network and systems control, management, security systems, and IIoT.

You should have prior knowledge and experience in power‑aware simulations with UPF verification and UVM testbench development.

You will be responsible for RTL SoC/Subsystem verification based on ARM CPUs and work on industry‑standard verification methodologies like UVM, Portable Stimulus, and Formal verification flows. You will report to the Director of Engineering, Verification.

Key Responsibilities

• Execute power‑aware simulations and debug failures related to power intent.
• Integrate UPF with UVM testbenches and VIPs.
• Verify design at RTL (SOC) level and gate‑level simulation.
• Create directed and constrained‑random tests for low‑power scenarios.
• Verify isolation, retention save/restore, and reset behavior across power domains.
• Develop assertions and functional coverage for power states and transitions.
• Support power‑aware regression and sign‑off.
• Use scripting languages (Make, Perl, Python, Shell).
• Collaborate with RTL and power architects.

Qualifications

• 10+ years of experience with strong hands‑on experience with SystemVerilog & UVM.
• Solid understanding of UPF / power intent modeling.
• Experience with power‑aware simulation.
• Knowledge of power domains & power states, reset vs power interactions.
• Strong debug skills across RTL, UPF, and testbench.
• Academic credentials: BE/BTech or MTech degree in EE/EECS/CS or equivalent.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non‑disqualifying physical or mental disability, national origin, veteran status, or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.