Platform Integration Engineer

Intel; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Intel is seeking an experienced Platform Integration Engineer for the Chassis Group in Bangalore, India. This role involves working closely with SoC architecture teams, designing high-performance networks-on-chip, and coordinating with IP development teams to ensure chassis requirements are met.

The ideal candidate will possess a Bachelor's/Master's degree in Science or Electrical Engineering and at least 6 years of relevant experience including expertise in Verilog/System Verilog. This position offers a dynamic work environment and opportunities to lead in innovative projects.

Qualifications

• 6+ years of experience in SOC and/or IP design.
• 5+ years' experience in microarchitecture and design IP systems, including 2+ years' in fabric design/integration.
• Good understanding of floorplan limitations.

Responsibilities

• Work with SoC architecture teams to understand chassis requirements.
• Design high-performance networks-on-chip that meet SoC PPA requirements.
• Coordinate with foundation IP development team within the Chassis Group.

Skills

Verilog/System Verilog Design

Microarchitecture and design IP systems

AMBA protocols (CHI, AXI, AHB, APB)

PCIe/CXL

Communication skills

Education

Bachelor's/Master's degree in Science, Electrical Engineering or equivalent

Job description

Job Details

Intel is seeking an experienced Platform Integration Engineer for the Intel Chassis Group. The Chassis Group is chartered to deliver the chassis for multiple SoCs within Intel. The role involves

• Working with the SoC architecture teams to understand the SoC chassis requirements
• Designing and developing high-performance networks‑on‑chip which meet the SoC PPA requirements using chassis foundation library components
• Coordinating with the foundation IP development team within the Chassis Group to modify/create IP components as per SoC needs

Qualifications

• Bachelor's/Master's degree in Science, Electrical Engineering or equivalent
• 6+ years of experience in SOC and/or IP design
• 5+ years' experience in microarchitecture and design IP systems, including 2+ years' experience in fabric design/integration
• Expertise in Verilog/System Verilog Design, Lint/CDC/RDC and timing constraints
• Good understanding of AMBA protocols (CHI, AXI, AHB, APB) and PCIe/CXL
• Experience in analyzing power, performance and area trade-offs in designs
• Ability to work with physical design to understand floorplan limitations
• Communication skills
• Capacity to work with geographically distributed engineering teams across multiple time zones.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Business Group

The Central Engineering Group (CEG) is Intel's data‑driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer‑driven, end‑to‑end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.