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Semiconductor Engineering in Bengaluru, India, seeks an experienced timing-closure engineer to optimize clock tree, ensure signoff, and push margins at 7nm and below. You will drive complex timing closures, collaborate with signoff teams, and own critical constraints.
You will mentor junior engineers, review floorplans, and explain tradeoffs to colleagues in the US, helping projects move forward and catching issues early in the process.
You are the person teams turn to when timing closure looks impossible and the clock tree feels like a puzzle with missing pieces. You know the difference between a design that passes signoff and one that ships with margin to spare, because you have spent years making those calls at 7nm and below. You do not just push buttons in ICC2 or PrimeTime—you know why a constraint matters, and you catch issues before they ripple downstream. When someone asks about integrating a tricky mixed-signal macro, you have a mental toolkit of what can go wrong and how to make it work. You thrive on the hard problems: GHz-level timing, power optimization, and the reality of silicon bring-up. You want your work to show up in real products, not just in a tapeout report. Sharing what you know is second nature—mentoring junior engineers, reviewing a teammate’s floorplan, or explaining a tradeoff to a colleague in the US. You care about getting the details right, but you do not get stuck in them. You move projects forward, ask the right questions, and always look for a better way to do things.