Staff Engineer, ASIC Physical Design

1840 Micron Tech. OP India LLP; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

1840 Micron Tech. OP India LLP in Bengaluru, India is looking for a physical design engineer with a strong background in implementing design solutions for SSD groups. Candidates should have at least 8 years of experience in physical design and proficiency with Cadence tools.

The role involves various responsibilities such as block-level design, timing closure, and physical verification processes. A degree in electronics or computer architecture is required. Strong commitment and time management skills are essential.

Qualifications

• Minimum of 8 years of hands‑on physical design implementation experience.
• Experience with advanced process technology nodes (5nm/3nm preferred).
• Track record of successfully closing all IR issues within a block.

Responsibilities

• Work on processors, controller architectures or ASICs for SSD Group.
• Perform low‑power aware floorplanning, placement, and routing.
• Conduct RC extraction, STA timing closure, and IR/EM analysis.

Skills

Physical design implementation

PPA analysis

STA closure

Cadence layout tools

Physical verification

Digital electronics fundamentals

English proficiency

Analytical skills

Education

Bachelor’s or Master’s degree in electronics, computer architecture, or related field

Tools

Cadence Innovus

Cadence Tempus

Caliber

Job description

Responsibilities

The team member will typically work on processors, controller architectures or ASICs for the Enterprise SSD Group. Duties include block-level low‑power aware floorplanning, placement, clock‑tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, and tape‑out activities.

Requirements

• Minimum of 8 years of hands‑on physical design implementation experience along with APR flow development, PPA analysis, and STA closure at block level.
• Experience with advanced process technology nodes (5nm/3nm preferred).
• Proficiency with Cadence layout tools such as Innovus and Tempus.
• Hands‑on experience in physical verification closure (DRC/LVS/antenna) using Caliber.
• Track record of successfully closing all IR issues within a block based on feedback.
• Strong fundamentals in digital electronics and microprocessors.
• Excellent analytical skills.
• English language proficiency, strong collaboration and interpersonal skills.
• Strong ownership, commitment and time‑management abilities.
• Bachelor’s or Master’s degree in electronics, computer architecture, or related field.

Preferred Skills

• Strong verbal communication skills.
• Experience with Cadence PnR tools.
• Formal verification experience.
• Deep knowledge of digital electronics and microprocessors.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.