IO and Mixed Signal Circuit Design Engineer

Broadcom Inc.; Bengaluru; On-site; INR 1,800,000 - 2,900,000; Full time

Job summary

Broadcom Inc. in Bengaluru is seeking a senior engineer to design and verify IO interfaces and mixed-signal blocks using advanced CMOS technologies. You will implement analog circuits such as PLLs and bandgaps, and work closely with layout and test teams for silicon validation.

We require MSEE with 5–15 years of hands-on experience, proficiency in Cadence Virtuoso/ADE, and strong SPICE simulator skills. Strong communication across geographies is essential.

Qualifications

• MSEE with 5–15 years hands-on mixed-signal design.
• Experience with analog blocks: PLLs, LDOs, Bandgap, ADCs/DACs.
• Proficiency in Cadence Virtuoso and ADE; SPICE simulators.

Responsibilities

• Design and verification of IO interfaces and mixed-signal blocks.
• Interface with layout engineers and oversee physical design and verification.
• Develop models and timing characterization of cells.
• Create datasheets and integration guides for silicon.
• Support silicon validation on test chips and with test engineers.

Skills

Analog design

PLL design

LDO design

5nm/3nm CMOS

Schematic capture

Cadence Virtuoso

ADE

Spectre/HSPICE

LVS/DRC verification

Shell scripting

Education

MSEE

5-15 years experience

Tools

Cadence Virtuoso Schematic Capture

Cadence ADE

Spectre

HSPICE

Totem/Pathfinder

Job description

Please Note:1. If you are a first time user, please create your candidate login account before you apply for a job.2. If you already have a Candidate Account, please Sign-In before you apply.Job Description:Work as part of Mixed Signal and IO Library Development team in Central Engineering. Primary responsibilities include:Design and verification of IO interfaces and mixed signal blocks such as POR, process monitors, voltage/temperature sensors, crystal oscillators etc.RTL coding, synthesis and verification of digital wrappers that interface with analog circuitryInterface with both custom and P&R layout engineers and oversee physical design and verification.Develop functional models and perform timing characterization of these cells.Directly interface with end customers to understand their requirements, come up with specifications and implement circuit designs that support them.Create necessary infrastructure and generate test vectors to support silicon validation of these blocks on test chips.Work with test engineers to support silicon validation either on ATE or on the bench.Develop accurate documentation in the form of datasheets, application notes and integration guidesSkills and Qualifications Required:Educational requirements: MSEE with a minimum of 5-15 years of hands-on experience in independently designing mixed signal circuits especially in newer CMOS technologies such as 5nm or 3nmMust have experience in designing analog circuits such as PLLs, LDOs, Bandgap references, ADCs or DACs-knowledge of AMS methodology and analog circuit modeling will be a plusMust be proficient with Cadence Virtuoso Schematic Capture and ADE along with an excellent knowledge of spice based simulators such as Spectre and/or HspiceWorking knowledge of LVS, DRC along with EM/ESD verification tools such as Totem/Pathfinder/PERStrong written and oral communication skills in English to be able to work effectively across geographies as well as to be able to interface with end customersRequire proficiency in automation using shell scripting or any other languages such as SED, AWK, TCL or PERLˇBroadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.