Physical Design Engineer

Proxelera; Hyderabad, Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Proxelera is seeking a PD EMIR Engineer with 3-4 years of experience to lead IR drop and EM sign-off at the SoC level. The role will involve identifying high EMIR issues, debugging, and collaborating with the physical design team to drive IREM closure in a Bangalore/Hyderabad environment.

Ideal candidates have 3+ years in PDN/EMIR closure for digital ASICs, deep knowledge of PDN/EMIR impacts, and proficiency with Redhawk for static/dynamic analysis and vectorless approaches.

Qualifications

• 3+ years of experience in PDN/EMIR closure for digital ASICs.
• Own SoC level IR drop, signal and power EM sign-off.
• Identify issues causing high EMIR, debug and provide optimal solutions.

Responsibilities

• Own SoC level IR drop, signal and power EM sign-off.
• Identify issues causing high EMIR, debug and provide optimal solutions.
• Collaborate with physical design team to drive IREM closure.

Skills

EMIR closure experience

IR drop analysis

Issue debugging & solutions

Tools

Redhawk tools

Job description

Job Description

Job Title: PD EMIR Engineer - 3-4 Yrs

Location: Bangalore/ Hyderabad

Experience required: 3-4 Years

The Job Role:

• Top 3 skills: "More than 3 years of experience in PDN/EMIR closure in digital ASIC chips."
• Own SoC level IR drop, Signal and power EM sign-off
• Identify issues causing high EMIR, debug and optimal provide solutions

Key Responsibilities:

• Own SoC level IR drop, Signal and power EM sign-off
• Identify issues causing high EMIR, debug and optimal provide solutions.
• Closely co-work with physical design team, to drive IREM closure

Preferred Experience:

• More than 3 years of experience in PDN/EMIR closure in digital ASIC chips. Preferred 8+ years or more years of experienc
• Knowledgeable in physical design flow and impact of different aspects of designs causing IR EM issues
• Expert in usage of Redhawk tools for static/Dynamic analysis using vectorless/vector approach and PG EM and Signal EM analysis,
• Involved in Tape-in of multiple SoCs

Preferred candidate profile

Perks and benefits