Lead ASIC PD / EMIR Engineer

SmartSoC Solutions Pvt Ltd; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

SmartSoC Solutions Pvt Ltd is hiring a Lead ASIC PD / EMIR Engineer in Bengaluru to tackle power integrity and sign-off for advanced digital SoCs. You will own SoC-level IR Drop, EMIR closure, and collaborate with the Physical Design team to drive robust PDN analysis and reliable sign-off.

The candidate should have 8+ years in VLSI/Physical Design and 3+ years in PDN/EMIR closure for digital ASICs, with strong debugging and cross-functional collaboration skills.

Qualifications

• Must have 8+ years in VLSI/Physical Design
• At least 3+ years in PDN and EMIR closure for digital ASICs
• Strong expertise in EMIR analysis and sign-off methods
• Excellent debugging, analytical and cross-functional collaboration skills

Responsibilities

• Own SoC-level IR drop, Signal EM, and Power EM sign-off for complex digital ASIC designs
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations
• Debug EMIR issues and provide optimized, practical solutions to achieve sign-off
• Collaborate with Physical Design team to drive efficient IR/EM closure across the chip
• Analyze PDN and recommend improvements for robust power integrity
• Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets

Skills

VLSI/PD

PDN closure

EMIR analysis

Debugging & collaboration

Job description

We're Hiring | Lead ASIC PD / EMIR Engineer

Are you passionate about power integrity and sign-off for advanced digital SoCs? We're looking for an experienced PDN / EMIR Engineer to join our growing VLSI team.

Required Experience

• 8+ years of overall VLSI/Physical Design experience is preferred.
• 3+ years of hands‑on experience in PDN and EMIR closure for digital ASIC designs.
• Strong expertise with industry‑standard EMIR analysis and sign‑off methodologies.
• Excellent debugging, analytical, and cross‑functional collaboration skills.

Key Responsibilities

• Own SoC‑level IR Drop, Signal EM, and Power EM sign‑off for complex digital ASIC designs.
• Drive EMIR closure by identifying root causes of power integrity and electromigration violations.
• Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign‑off.
• Collaborate closely with the Physical Design (PD) team to drive efficient IR/EM closure across the chip.
• Analyze power delivery networks (PDN) and recommend improvements for robust power integrity.
• Ensure timely closure of EMIR sign‑off while meeting performance, power, and reliability targets.