Physical Design Engineer

ACL Digital; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

A leading IT consulting and engineering firm in Bengaluru is seeking a skilled Physical Design Engineer. The ideal candidate will have over 4 years of experience in ASIC physical design, specializing in RTL-to-GDSII implementation. Responsibilities include optimizing performance, power, and area through extensive collaboration with various teams. Competitive compensation offered with full-time employment.

Qualifications

• 4+ years of experience in ASIC physical design.
• Strong hands-on experience with physical design tools.
• Solid grasp of power grid design and physical verification flows.

Responsibilities

• Own block-level or full-chip implementation from RTL to GDSII.
• Perform floorplanning and placement.
• Drive physical verification and signoff.

Skills

Physical design concepts: floorplan

Placement

Clock tree synthesis (CTS)

Routing and optimization

Timing analysis

Familiarity with Tcl, Perl, Python

Education

B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design

Tools

EDA tools

Job description

Direct message the job poster from ACL Digital

Job Title

Physical Design Engineer

Experience

4+ Years

Employment Type

Full-time

Job Summary

We are looking for a skilled and motivated Physical Design Engineer to join our backend implementation team. The engineer will be responsible for RTL-to-GDSII implementation of complex SoC blocks or full-chip designs, targeting performance, power, and area (PPA) optimization and signoff closure.

Key Responsibilities

• Own block-level or full-chip implementation from RTL to GDSII.
• Perform:
• Floorplanning and placement
• Clock tree synthesis (CTS)
• Routing and optimization
• Run and close timing (STA), IR drop, EM, DRC, LVS, and antenna checks.
• Drive physical verification and signoff across various corners and scenarios.
• Collaborate with RTL, DFT, STA, and power teams for successful integration.
• Implement and debug low-power design techniques (UPF/CPF-based flows).
• Apply congestion analysis, ECOs, and timing fixes across critical paths.
• Optimize for performance, power, and area using EDA tools and foundry guidelines.
• Prepare design reports and support tapeout activities.

Required Skills and Experience

• B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
• 4+ years of experience in ASIC physical design.
• Strong hands-on experience with tools like:
• Good understanding of physical design concepts: floorplan, placement, CTS, routing, ECO, and signoff.
• Familiarity with scripting languages: Tcl, Perl, Python for flow automation.
• Solid grasp of timing analysis, power grid design, and physical verification flows.

Contact

Interested can share Cv to [e-mail]

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Engineering, Product Management, and Project Management

Industries

• IT Services and IT Consulting
• Semiconductor Manufacturing
• Engineering Services