Physical Design Director ( Hyderabad )

Mulya Technologies; Hyderabad; On-site; INR 400,000 - 700,000; Full time

Job summary

Mulya Technologies in Hyderabad seeks a senior Physical Design Director to lead and grow the PD function. You will drive end-to-end physical implementation of high-speed connectivity ASICs, building a high-performance PD team and establishing best-in-class design flows.

The role partners with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon success. The ideal candidate combines deep hands-on PD expertise at advanced nodes with a track record of tapeouts and the

Qualifications

• Bachelor's or master's degree in electrical engineering, Electronics, or Computer Science.
• 18+ years of experience in ASIC design.
• Strong leadership and team-building capabilities.

Responsibilities

• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII.
• Drive floor planning, placement, CTS, routing, timing closure, power analysis, and physical verification (DRC/LVS).
• Lead timing closure across multiple corners and modes at advanced nodes (5nm and below).
• Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability targets.
• Manage tapeout schedules, milestones, and cross-functional dependencies to deliver on time and within PPA targets.
• Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass success.
• Evaluate and deploy EDA tools; drive automation (Tcl, Python, Perl) to improve turnaround time and quality.
• Collaborate with EDA vendors on tool evaluation, adoption, and methodology improvements.

Skills

Leadership

PD Engineering

Team Building

Power Integrity

CAD/METHODOLOGY

Education

Bachelor's or Master’s in Electrical Eng / Electronics / CS

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime

Calibre

RedHawk/Voltus

StarRC

Job description

Top40 Semiconductor Organization in the world

We provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, We enable organizations to unlock the full potential of modern AI. ’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements.

Role Overview

We are seeking a Physical Design Director to lead and grow our Physical Design function in Hyderabad. This is a senior leadership role responsible for building and managing a high-performing PD team, driving physical implementation of complex, high-speed connectivity ASICs, and establishing best-in-class design methodology and flows.

The ideal candidate brings deep hands-on expertise in full-chip physical design at advanced nodes, a proven track record of successful tapeouts, and the leadership ability to scale a team and deliver results in a fast-paced, high-growth environment. This role will work closely with global PD, RTL, DV, DFT, and packaging teams to ensure first-pass silicon sucss.

Key Responsibilities

Leadership & Team Building

• Build, lead, and mentor a high-performing Physical Design team in Hyderabad across PnR, STA, EMIR/Power Integrity, and CAD/methodology fun
• ctionsDefine team structure, hiring roadmap, and career development paths for PD eng
• ineersFoster a culture of technical excellence, ownership, and continuous impro
• vementPartner with global PD leadership (US and Israel sites) to align on strategy, methodology, and execution priorities

Physical Design Execution

• Own end-to-end physical implementation of complex SoCs/ASICs from floor planning through GDSII
• signoffDrive floor planning, placement, clock tree synthesis (CTS), routing, timing closure, power analysis (IR drop/EM), and physical verification (D
• RC/LVS)Lead timing closure across multiple corners and modes (MMMC), ensuring robust STA signoff at advanced nodes (5nm and
• below)Oversee power integrity and reliability analysis (IR drop, EM) to meet design quality and manufacturability
• targetsManage tapeout schedules,milestones, and cross-functional dependencies to deliver on time and within PPAtargetsMethodology & amp; CAD
• Establish and continuously improve PD flows, methodologies, checklists, and best practices for first-pass
• successEvaluate and deploy EDA tools (Cadence Innovus, Synopsys Fusion Compiler, PrimeTime, Calibre, RedHawk/Voltus, StarRC, etc.)Drive automation and scripting (Tcl, Python, Perl) to improve turnaround time and design
• qualityCollaborate with EDA vendors on tool evaluation, adoption, and methodology improvements

Cross-Functional Collaboration

• Partner closely with RTL, DV, DFT, packaging, and architecture teams to enable seamless integration of complex subsystems (SerDes, high-speed PHYs, die-to-die interfaces, etc.)Provide physical design input during architecture and floorplan feasibility studies, die sizing, and IP evaluationRepresent the Hyderabad PD team in global design reviews, tapeout readiness reviews, and leadership forums

Basic Qualifications

• Bachelor's or master’s degree in electrical engineering, Electronics, or Computer Science18+ years of experience in ASIC