PD Lead

LeadSOC Technologies Pvt Ltd; Bengaluru South; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

LeadSoc Technologies Pvt Ltd in Bengaluru South is seeking a PD Lead to drive physical design for complex SoC/ASIC/FPGA projects on-site. You will manage floorplanning, synthesis, place & route, timing closure, power optimization, and sign-off, coordinating with multi-disciplinary teams and guiding junior engineers.

You should be proficient with Cadence/Synopsys/Mentor PD flows and scripting (TCL/Perl/Python), and have strong VLSI fundamentals and RTL-to-GDSII experience.

Qualifications

• Expertise in physical design flows including floorplanning, synthesis, place and route, clock tree synthesis, timing closure, and sign-off.
• Experience with standard PD tools (Cadence, Synopsys, Mentor) and scripting for automation (TCL, Perl, Python).
• Knowledge of VLSI fundamentals, digital design, RTL-to-GDSII, power integrity, signal integrity, and DfT/DfM concepts.
• Experience collaborating with cross-functional teams, managing project schedules, reviewing technical deliverables, and mentoring junior engineers.
• Strong analytical, problem-solving, and documentation skills; ability to interpret complex reports and make data-driven decisions.
• Academic background in Electronics, Electrical Engineering, Computer Engineering, or related discipline.

Responsibilities

• Lead physical design activities across complex SoC/ASIC/FPGA projects.
• Oversee floorplanning, synthesis, place and route, timing closure, power optimization, and sign-off.
• Collaborate with front-end, verification, analog, and software teams; communicate progress to clients and stakeholders.
• Guide junior engineers, review constraints/scripts, analyze reports, and drive improvements in PD methodologies.

Education

Bachelor’s or Master’s degree in Electronics / Electrical Engineering / Computer Engineering or related discipline

Tools

Cadence

Synopsys

Mentor

TCL

Perl

Python

Job description

Company Description LeadSoc Technologies Pvt Ltd delivers cutting-edge engineering design services in VLSI and Embedded Systems for Semiconductor, Automotive, Telecom, and Consumer Electronics industries. Over the past nine years, the company has grown rapidly, providing end-to-end VLSI design services from micro-architecture to tape-out, including post-silicon support and co-development of multiple SoC releases. LeadSoc operates in-house VLSI and embedded labs equipped with state-of-the-art EDA tools and diverse reference boards to enable continuous learning, innovation, and proof-of-concept development. The organization’s capabilities span SoCs, FPGA, ASIC, RF, and board design, as well as platform software, middleware, applications, HMI, IoT, and cloud solutions on AWS, GCP, and Azure. Teams at LeadSoc also support diagnostics, validation, performance optimization, and migration of software stacks from legacy to next-generation platforms.
Role Description The PD Lead is a full-time, on-site role based in Bengaluru South, responsible for leading physical design activities across complex SoC, ASIC, or FPGA projects. This role oversees floorplanning, synthesis, place and route, timing closure, power optimization, and sign-off, ensuring design quality and adherence to project schedules. The PD Lead collaborates closely with front-end, verification, analog, and software teams to define implementation strategies, resolve integration issues, and support silicon bring-up when required. Daily tasks include guiding junior engineers, reviewing constraints and scripts, analyzing reports, coordinating EDA tool usage, and driving continuous improvement in physical design flows and methodologies. The position also involves regular interaction with clients and internal stakeholders to communicate progress, manage risks, and align physical design deliverables with overall product goals.
Qualifications

• Candidates should possess strong expertise in physical design flows, including floorplanning, synthesis, place and route, clock tree synthesis, timing closure, and sign-off.
• Candidates should possess skills in working with standard EDA tools for PD (e.g., Cadence, Synopsys, Mentor) and scripting languages such as TCL, Perl, or Python for automation.
• Candidates should possess knowledge of VLSI fundamentals, digital design, RTL-to-GDSII processes, power integrity, signal integrity, and DfT/DfM concepts.
• Candidates should possess experience collaborating with cross-functional teams, managing project schedules, reviewing technical deliverables, and mentoring junior engineers.
• Candidates should possess strong analytical, problem-solving, and documentation skills, with the ability to interpret complex reports and make data-driven decisions.
• Relevant academic background such as a Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.