Design Verification Engineer SystemVerilog UVM BB50FT RM 4458

Source-Right; Hyderabad; On-site; INR 900,000 - 1,200,000; Full time

Job summary

Source-Right is seeking a Design Verification Engineer (SystemVerilog/UVM) in Hyderabad to verify PCIe IP/sub-systems with AXI/AHB interfaces. Ideal candidates have 5+ years of relevant experience and strong UVM SV testbench skills.

You will develop verification plans, build testbenches, and debug intricate issues while collaborating with ASIC teams to ensure quality and timely delivery.

Qualifications

• Expert PCIe IP/sub-systems verification experience.
• AXI protocol experience is mandatory.
• Expert at defining block/sub-system verifications.
• Expert level in UVM SV testbench development.
• Education: B.S. in electrical engineering or CS with industry experience.

Responsibilities

• Develop and maintain UVM-based SV testbenches for PCIe IP.
• Verify PCIe, AXI/AHB interfaces with complex workloads.
• Define verification plans and coverage metrics.
• Debug complex verification issues with cross-functional teams.
• Collaborate with ASIC teams to ensure quality and on-time delivery.

Skills

IP/Block/Subsystem Verification

SystemVerilog

UVM Verification

UVM Testbench Development

AXI/AHB Interfaces

PCIe/NVMe Protocol Verification

Perl/Python Scripting

Education

B.S. in Electrical Engineering or Computer Science

Job description

Job Description

Position: Design Verification Engineer (SystemVerilog/UVM) (BB50FT RM 4458)

• Candidate Skill: IP/Block/Subsystem Verification, RTL Front-End Verification
• Years of Experience/Expectations: Minimum 5 Years
• Mandatory/Optional: Mandatory
• Candidate Skill: SystemVerilog (SV), UVM Verification, UVM Testbench Development
• Years of Experience/Expectations: Minimum 4 Years
• Mandatory/Optional: Mandatory
• Candidate Skill: AXI, AHB Interfaces, Bus Protocol Verification
• Years of Experience/Expectations: Minimum 2 Years
• Mandatory/Optional: Mandatory
• Candidate Skill: PCIe, NVMe Protocol Verification
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Mandatory
• Candidate Skill: Perl, Python Scripting, Verification Automation
• Years of Experience/Expectations: Minimum 1 Year
• Mandatory/Optional: Optional

Job Description

• An expert level experience with PCIe IP/sub-systems.
• AXI protocol is mandatory
• Highly experienced with defining block, sub-system.
• An expert level with developing UVM-based SV test-benches.
• Deep understanding and knowledge of verification methodologies flows and quality metrics.
• Great debugging and problem-solving skills.
• Team player with great interpersonal communication skills.

Job Qualifications

• At least 3-6 years of relevant experience in PCIe verification.
• Strong and relevant expertise with ASIC simulation tools and advanced verification methods.
• Expert level in verification languages such as UVM and System Verilog.
• Relevant experience with writing block-level .
• Education: B.S. in electrical engineering, computer science with extensive industry experience.

Skills Required

• IP/Block/Subsystem Verification (RTL Front end verification) – minimum 5 years
• SV, UVM Verification – minimum 4 Years
• Interfaces (AXI/AHB) – minimum 2 years
• Protocols (DDR/Onfi/PCIE/NVMe) – minimum 2 years
• Scripting (Perl/Python) – Optional