PCIe Formal Verification Engineer

Gtc Informatics Private Limited; India; Remote; INR 1,200,000 - 1,800,000; Full time

Job summary

GTC Informatics Private Limited urgently hires experienced PCIe Formal Verification Engineers for semiconductor design and verification projects across India.

This PAN INDIA role requires 4–10 years in VLSI/ASIC/SoC verification and hands-on use of formal tools to prove PCIe IPs.

Qualifications

• 4–10 years of experience in VLSI/ASIC/SoC verification.
• Hands-on experience with formal verification techniques.
• Solid knowledge of the PCIe protocol and related IPs.
• Experience with SystemVerilog Assertions (SVA).
• Familiarity with JasperGold, VC Formal and Questa Formal.

Responsibilities

• Carry out formal verification of PCIe IPs and subsystems.
• Write SVA properties, assertions, constraints and cover points.
• Run formal tools and close proofs.
• Debug counterexamples and coordinate with RTL teams to fix issues.
• Track formal coverage and support verification sign-off.
• Collaborate with design and DV teams on client projects.

Skills

Formal verification

SystemVerilog Assertions

PCIe protocol knowledge

Debugging

Communication skills

Tools

JasperGold

VC Formal

Questa Formal

Job description

About the Role:

GTC Informatics Private Limited is urgently hiring experienced PCIe Formal Verification Engineers for semiconductor design and verification projects across India. This is a priority role, and we encourage suitable candidates to apply immediately.

Location : PAN INDIA

Roles & Responsibilities:

• Carry out formal verification of PCIe IP and subsystems
• Write SVA properties, assertions, constraints and cover points
• Run formal tools and close proofs
• Debug counterexamples and work with RTL design teams to fix issues
• Track formal coverage and support verification sign-off
• Work closely with design and DV teams on client projects

Required Skills & Experience:

• 4–10 years of experience in VLSI / ASIC / SoC verification
• Strong hands-on experience in formal verification
• Good knowledge of the PCIe protocol
• Experience with SystemVerilog Assertions (SVA)
• Experience with formal tools such as JasperGold, VC Formal or Questa Formal
• Good debugging and communication skills

Good to Have:

• Exposure to DV, RTL design or DFT
• Experience with PCIe Gen4/Gen5