Lead Design Verification Engineer

Tech Mahindra; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Tech Mahindra Silicon Engineering in Bengaluru is seeking a Design Verification Engineer with 3–6 years of ASIC/SoC verification experience to verify high‑performance IPs, subsystems, and SoCs using SystemVerilog/UVM and robust test plans for PCIe compliance.

You will work with Architecture, RTL, Firmware, Validation and Verification teams to build strong environments, automate tests, and push silicon quality for global clients.

Qualifications

• 3–6 years of ASIC/SoC design verification experience.
• Strong fundamentals in digital design and verification.
• Hands-on with SystemVerilog, UVM, functional verification, constrained random, and SVA.
• PCI Express (PCIe) protocol knowledge.
• Experience with Cadence Xcelium, Synopsys VCS, Mentor QuestaSim.
• Scripting in Python, Perl, Tcl, or Shell.
• Excellent debugging and problem-solving skills.
• Strong communication and teamwork.

Responsibilities

• Develop and execute verification plans for IP, subsystem, and SoC designs.
• Build and maintain SystemVerilog/UVM-based verification environments.
• Create directed and constrained-random test cases.
• Verify PCI Express (PCIe) protocol functionality and compliance.
• Develop scoreboards, checkers, assertions, and coverage models.
• Analyze simulation failures, debug RTL with design teams.
• Drive functional, code, assertion, and toggle coverage closure.
• Participate in architecture, design, and verification reviews.
• Develop automation scripts to improve verification productivity.
• Support subsystem and SoC integration verification activities.
• Perform regression execution, failure analysis, and bug tracking.
• Collaborate with cross-functional teams to ensure silicon quality.

Skills

SystemVerilog

UVM

Functional verification

Constrained random

Assertion-based verification

PCIe protocol

Python scripting

Waveform debugging

Education

BE/BTech/ME/MTech in Electronics, Electrical, VLSI, Microelectronics, Computer Engineering

Tools

Cadence Xcelium

Synopsys VCS

Mentor QuestaSim

Job description

Brief About Tech Mahindra – Silicon Engineering

Tech Mahindra Silicon Engineering is a key part of Tech Mahindra's semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, and industrial clients. The practice focuses on VLSI, embedded systems, and platform engineering, supporting customers from architecture and design through verification, validation, and sustenance engineering.

The Silicon Engineering unit works across IP, Subsystem, and SoC-level development, offering capabilities in areas such as Design Verification, RTL Design, DFT, Physical Design, Post-Silicon Validation, Embedded Software, Emulation, and System Modeling & Simulation. Teams leverage industry-standard methodologies, tools, and verification frameworks to deliver high-quality, production-ready silicon solutions.

Backed by Tech Mahindra's global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology companies worldwide, operating as an extended engineering arm to accelerate innovation, reduce time-to-market, and ensure reliable, scalable silicon platforms. It is part of Tech Mahindra's broader engineering-led growth strategy serving multiple global industries.

About the Role

We are seeking a talented and motivated Design Verification Engineer with 3–6 years of experience in ASIC/SoC verification and working knowledge of the PCI Express (PCIe) protocol. In this role, you will be responsible for verifying high-performance IPs, subsystems, and SoCs using industry-standard verification methodologies while ensuring functional correctness, protocol compliance, and coverage closure.

You will work closely with Architecture, RTL Design, Firmware, Validation, and Verification teams to develop robust verification environments, execute comprehensive test plans, and debug complex functional issues. This role offers an opportunity to work on next‑generation semiconductor products and cutting‑edge verification technologies.

Key Responsibilities

• Develop and execute comprehensive verification plans for IP, subsystem, and SoC‑level designs.
• Build and maintain System Verilog/UVM‑based verification environments.
• Create directed and constrained‑random test cases to validate design functionality.
• Verify and debug PCI Express (PCIe) protocol functionality and compliance requirements.
• Develop and maintain scoreboards, checkers, assertions, and functional coverage models.
• Analyze simulation failures, debug RTL issues, and collaborate with design teams for resolution.
• Drive functional, code, assertion, and toggle coverage closure.
• Participate in architecture, design, and verification reviews.
• Develop automation scripts and methodologies to improve verification productivity.
• Support subsystem and SoC integration verification activities.
• Perform regression execution, failure analysis, and bug tracking.
• Collaborate with cross‑functional teams to ensure successful project execution and silicon quality.

Qualifications

• BE/BTech/ME/MTech degree in Electronics, Electrical, VLSI, Microelectronics, Computer Engineering, or related disciplines.

Required Skills

• 3–6 years of experience in ASIC/SoC Design Verification.
• Strong understanding of digital design fundamentals and verification methodologies.
• Hands‑on experience with: SystemVerilog, UVM, Functional Verification, Constrained Random Verification, Assertion‑Based Verification (SVA)
• Working knowledge of PCI Express (PCIe) protocol.
• Strong debugging skills using waveform analysis and simulation tools.
• Experience with industry‑standard simulators such as: Cadence Xcelium, Synopsys VCS Mentor QuestaSim
• Good understanding of IP, subsystem, and SoC verification flows.
• Scripting experience in Python, Perl, Tcl, or Shell.
• Strong analytical, debugging, and problem‑solving skills.
• Excellent communication and collaboration skills.

Preferred Skills

• Experience with PCIe Gen4/Gen5 verification.
• Experience in IP, subsystem, or full‑chip verification.
• Knowledge of emulation, FPGA prototyping, or formal verification.
• Exposure to coverage‑driven verification methodologies.
• Familiarity with automation and verification framework development.
• Experience working with complex SoC architectures.