PCI Express (PCIe) Verification Engineer

Tech Mahindra Limited; Bengaluru; On-site; INR 1,200,000 - 2,000,000; Full time

Job summary

Tech Mahindra Silicon Engineering seeks a PCIe Verification Engineer with 4-6 years of hands-on DV experience. You will verify PCIe controller/IP designs at IP and subsystem levels, ensuring protocol compliance and robust verification environments, alongside RTL and SoC teams.

The role focuses on PCIe protocol, SystemVerilog, UVM, constrained-random verification, and coverage-driven strategies to achieve verification closure across modules and interfaces.

Qualifications

• 4-6 years of hands-on Design Verification experience.
• Strong proficiency in SystemVerilog and UVM.
• Strong understanding and hands-on verification experience with PCIe protocol.
• Experience with PCIe Gen3/Gen4 (Gen5 exposure desirable).

Responsibilities

• Develop and execute PCIe IP/Sub-System Verification plans, testbenches, and environments.
• Develop reusable verification components using SystemVerilog and UVM.
• Create directed and constrained-random PCIe test scenarios and sequences.
• Verify PCIe functionality across TL, DL, and link layers.
• Verify features including TLP handling, config transactions, flow control, LTSSM, and error handling.
• Develop verification test plans based on PCIe specs and designs.
• Develop and integrate SystemVerilog Assertions for checking.
• Maintain UVM sequences, drivers, monitors, checkers, scoreboards, and coverage models.
• Perform functional, code, assertion, and coverage analysis towards closure.
• Debug simulations and regressions using waveform analysis and logs.
• Collaborate with RTL designers to reproduce and resolve issues.
• Configure PCIe Verification IP within the environment.
• Support regression automation and verification infrastructure using scripting.

Skills

SystemVerilog

UVM

PCIe protocol

Verification

Constrained-random

RTL debugging

Education

BE/BTech/ME/MTech

Tools

VCS

Xcelium

QuestaSim

Job description

Brief About Tech Mahindra - Silicon Engineering

Tech Mahindra Silicon Engineering is a key part of Tech Mahindra's semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, and industrial clients. The practice focuses on VLSI, embedded systems, and platform engineering, supporting customers from architecture and design through verification, validation, and sustenance engineering.

The Silicon Engineering unit works across IP, Subsystem, and SoC-level development, offering capabilities in areas such as Design Verification, RTL Design, DFT, Physical Design, Post-Silicon Validation, Embedded Software, and System Modeling & Simulation. Teams leverage industry-standard methodologies, tools, and verification frameworks to deliver high-quality, production-ready silicon solutions.

Backed by Tech Mahindra's global engineering DNA, the Silicon Engineering practice collaborates with leading semiconductor and technology clients worldwide, operating as an extended engineering arm to accelerate innovation, reduce time-to-market, and ensure reliable and scalable silicon platforms.

About the Role

We are looking for a highly motivated PCI Express (PCIe) Verification Engineer with 4-6 years of experience to join our growing Silicon Engineering team. In this role, you will be responsible for functional verification of complex PCIe Controller/IP designs at IP and Subsystem levels, ensuring protocol compliance, functional correctness, and verification closure.

The ideal candidate should possess strong hands-on expertise in PCI Express protocol, SystemVerilog, UVM, constrained-random verification, functional coverage, and debugging. The engineer will work closely with architecture, RTL design, and SoC verification teams to develop robust verification environments, test plans, test cases, and coverage-driven verification strategies.

This role provides an exciting opportunity to work on PCIe-based next-generation semiconductor products and high-speed interfaces for global technology customers.

Key Responsibilities

• Develop and execute comprehensive PCIe IP/Sub-System Verification plans, testbenches, and verification environments.
• Develop reusable verification components using SystemVerilog and UVM methodology.
• Create directed and constrained-random PCIe test scenarios and sequences to achieve verification coverage goals.
• Perform verification of PCIe functionality across relevant Transaction Layer, Data Link Layer, and link-level functionality.
• Verify key PCIe features including TLP handling, configuration transactions, flow control, LTSSM/link training, error handling, and recovery mechanisms.
• Develop verification test plans based on PCIe specifications, design specifications, microarchitecture, and functional requirements.
• Develop and integrate SystemVerilog Assertions (SVA) for protocol and design-level checking.
• Develop and maintain UVM sequences, drivers, monitors, checkers, scoreboards, reference models, and functional coverage models.
• Perform functional, code, assertion, and coverage analysis and drive verification towards coverage closure.
• Debug simulation and regression failures using waveform analysis, logs, and protocol-level debugging.
• Work closely with RTL designers and architects to reproduce, analyze, and resolve functional and protocol issues.
• Integrate and configure PCIe Verification IP (VIP) within the verification environment, where applicable.
• Support regression automation and verification infrastructure using Python, Perl, Tcl, or Shell scripting.
• Support IP integration and Subsystem/SoC-level verification activities.
• Participate in design reviews, verification reviews, technical discussions, and verification sign-off activities.

Qualifications

BE/BTech/ME/MTech degree in Electronics, Electrical, Communication Engineering, Computer Science, or related engineering disciplines.

Required Skills

• 4-6 years of hands-on Design Verification experience, preferably at IP/Sub-System level.
• Strong proficiency in SystemVerilog and UVM.
• Strong understanding and hands-on verification experience with the PCI Express (PCIe) protocol.
• Good knowledge of PCIe architectural concepts including:

Data Link Layer

TLPs

LTSSM / Link Training

Configuration Space

Flow Control

• Hands-on experience with PCIe Gen3/Gen4, with Gen5 exposure desirable.
• Experience developing reusable UVM verification environments, sequences, monitors, checkers, scoreboards, and coverage models.
• Good knowledge of constrained-random verification, functional coverage, code coverage, and assertions.
• Experience with industry-standard simulation/debug tools such as VCS, Xcelium or QuestaSim.
• Strong ability to debug RTL, UVM testbench, simulation, regression, and protocol-related failures.