Opening for SOC Verification Lead - Bangalore/Hyderabad

UST; Bengaluru; Sur place; INR 1 200 000 - 1 500 000; Plein temps

Résumé du poste

A leading semiconductor company in Bangalore/Hyderabad is seeking a highly motivated SOC Verification Lead to join their team. The ideal candidate will develop and execute verification plans for complex System-on-Chip (SoC) designs while collaborating with design teams. Responsibilities include functional and performance verification, maintaining verification environments using UVM, and debugging simulation results. This is a full-time position at the mid-senior level.

Qualifications

• Experience in SOC verification and verification methodologies.
• Strong knowledge of UVM and SystemVerilog.
• Ability to debug simulation results and identify design issues.

Responsabilités

• Perform functional and performance verification of SoC designs.
• Create and maintain verification environments.
• Develop test benches and coverage models.
• Collaborate with design and architecture teams.

Connaissances

Functional and performance verification

UVM

SystemVerilog

C++

Debugging and analysis

Outils

Simulation tools

Emulation tools

Description du poste

Opening for SOC Verification Lead – Bangalore/Hyderabad

We are seeking a highly motivated and experienced SoC Verification Engineer to join our team. As a key member of the verification team, you will be responsible for developing and executing verification plans for complex System-on-Chip (SoC) designs.

Responsibilities:

• Perform functional and performance verification of SoC designs using simulation, emulation, and formal verification techniques. Develop and execute comprehensive tests for functional verification and performance verification at the core and SOC level.
• Create and maintain verification environments using industry-standard tools and methodologies (e.g., UVM).
• Develop test benches, test cases, and coverage models using UVM, SystemVerilog, and C++.
• Debug and analyze simulation results to identify and resolve design issues.
• Collaborate with design and architecture teams to understand design specifications and identify potential verification challenges.
• Participate in code reviews and contribute to the improvement of verification methodologies.

Please share your updated profile to [e-mail]

Regards,
Jaya

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Other

Industries

Semiconductor Manufacturing