OPC Engineer

Tata Electronics Limited; Dholera; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Tata Electronics Limited in India is seeking an OPC Engineer to develop, implement, and optimize Optical Proximity Correction solutions for advanced lithography nodes, collaborating with Design, Process Integration, Lithography, Mask Engineering, and Foundry teams.

Key tasks include MBOPC/RBOPC, creating OPC recipes, lithography simulations, PWQ, hotspot analysis, and RET development; you will help drive pattern fidelity and manufacturability.

Qualifications

• Master's or PhD in Electrical Engineering, Semiconductor Technology, Physics, or related disciplines.
• 2–10 years of OPC, lithography, and mask data preparation experience.
• Solid knowledge of DRC/LVS, MRC, and RET techniques.

Responsibilities

• Perform MBOPC and RBOPC for advanced technology nodes and generate OPC recipes.
• Conduct lithography simulations and analyze pattern fidelity across process windows.
• Execute PWQ and hotspot analysis; verify OPC and lithography using industry tools.
• Collaborate with Process and Foundry teams to address lithographic challenges.
• Analyze mask manufacturability issues and propose improvements.
• Support RET development including SRAF, SMO, ILT, PSM; drive workflow automation.
• Debug mask-related yield and manufacturability issues; document methods and reports.

Skills

MBOPC

RBOPC

OPC tools

lithography simulations

mask data prep

Python

Tcl

Shell scripting

Process Window concepts

Education

Master's or PhD in Electrical Engineering

Semiconductor Technology

Physics

Tools

ASML Brion solutions

Computational lithography

MRC / DRC/LVS tools

Job description

Job Summary

We are seeking a highly motivated OPC Engineer. The engineer will be responsible for developing, implementing, and optimizing Optical Proximity Correction (OPC) solutions to improve lithographic printability and ensure compliance with advanced process node requirements. The role involves close collaboration with Design, Process Integration, Lithography, Mask Engineering, and Foundry teams to achieve manufacturing yield and pattern fidelity goals.

Key Responsibilities

• Perform Model-Based OPC (MBOPC) and Rule-Based OPC (RBOPC) for advanced technology nodes.Generate and validate OPC recipes for critical semiconductor layers.


• Conduct lithography simulations and analyze pattern fidelity across process windows.


• Execute Process Window Qualification (PWQ) and hotspot analysis.Perform OPC verification and lithography checking using industry-standard EDA tools.


• Collaborate with Process and Foundry teams to understand lithographic challenges and develop corrective solutions.


• Analyze mask manufacturability issues and recommend improvements.


• Support RET (Resolution Enhancement Techniques) development including:Sub-Resolution Assist Features (SRAF)Source Mask Optimization (SMO)Inverse Lithography Technology (ILT)Phase Shift Mask (PSM)Drive continuous improvement of OPC methodologies and automation workflows.


• Debug and resolve mask-related yield and manufacturability issues.


• Document methodologies, best practices, and technical reports.

Required Qualifications

Master's or PhD degree in

• Electrical Engineering


• Semiconductor Technology


• Physics


• Related disciplines

Experience

2-10 Years (can be adjusted based on hiring level)

Strong understanding of

• Semiconductor manufacturing processes


• Optical lithography


• Mask synthesis and mask data preparation


• Process window concepts


• Computational lithography

Required Technical Skills

• Experience with OPC and RET tools from:


• ASML Brion solutions


• Equivalent computational lithography tools

Knowledge of

• DRC/LVS methodologies


• Pattern matching and hotspot detection


• Mask Rule Checking (MRC)


• Yield enhancement techniques

Scripting experience in

• Python


• Tcl


• Shell scripting

Preferred Qualifications

• Understanding of computational lithography and process modeling.


• Exposure to machine learning applications in OPC and hotspot detection.


• Familiarity with semiconductor foundry design rules and tapeout processes.