Mixed Signal Design Verification Engineer

Intel; Bengaluru; Hybrid; INR 900,000 - 1,300,000; Full time

Job summary

Intel Bangalore seeks an experienced Mixed Signal Design Verification Engineer to validate IPs such as PCIE, UCIE, and USB4/Type‑C PHYs. You will develop test benches, run simulations, and collaborate with cross‑functional teams to ensure high quality, robust designs.

You will apply SystemVerilog/UVM in IP verification, work with VCS, Xcelium, or Questa, and contribute to hierarchies of power and timing analyses on complex mixed signal blocks.

Qualifications

• Minimum 4+ years (Bachelors) or 3+ years (Masters) in ASIC/IP verification.
• Experience with mixed signal verification and IP verification.
• Proficiency with SystemVerilog/UVM/Verilog for verification.
• Hands-on with industry standard EDA tools for simulation/verification.

Responsibilities

• Perform functional verification of mixed signal logic components and analog behavioral modeling.
• Develop verification plans, test benches, and environments for coverage.
• Define and execute models to verify performance and timing; debug issues.
• Collaborate with digital/analog teams to refine features and document findings.
• Lead test plan reviews and maintain verification infrastructure and scripts.

Skills

SystemVerilog

UVM

Verilog

Python

Perl

Tcl

VCS

Xcelium

Questa

JTAG

IJTAG

CRI

APB

Education

Bachelor's in electronics and communication

Master's in ECE

Tools

Git

Perforce

Job description

The Role And Impact

As a Mixed Signal Design Verification Engineer, you will be instrumental in ensuring Intel's success in delivering innovative and high-quality mixed signal components. By leveraging your technical expertise in verification methodologies, you will validate and enhance the functionality of mixed signal IPs (example PCIE, UCIE, USB4/Type-C PHYs). Your work will directly contribute to Intel's leadership in cutting-edge technology, ensuring the performance, reliability, and efficiency of our products. This role offers a unique opportunity to collaborate with cross‑functional teams and contribute to the development of industry‑leading solutions.

Job Details

Job Description:

Key Responsibilities

• Perform functional verification of mixed signal logic components, including analog behavioral modeling, to ensure compliance with design specifications.
• Develop comprehensive IP verification plans, test benches, and environments to achieve thorough coverage of mixed signal microarchitecture specifications.
• Define and execute simulation models to verify design performance, analyze power and timing, and identify and resolve design bugs.
• Conduct root cause analysis and implement corrective measures to address failing tests in the pre silicon environment.
• Collaborate with digital and analog architects, RTL developers, and physical design teams to refine and optimize architectural and microarchitectural features.
• Lead technical reviews of test plans and validation proofs with design and architecture teams, ensuring meticulous documentation of findings and processes.
• Maintain and enhance functional verification methodologies, infrastructure, and tools to align with evolving industry standards and best practices.

Qualifications

Minimum Qualifications

• Bachelor's or Master's degree in electronics and communication or electrical engineering, VLSI Engineering, or a related field.
• 4+ years of experience with a Bachelor's degree, or 3+ years of experience with a Master's degree in ASIC or IP verification, subsystem and function coverage.
• Proficiency in mixed signal verification and hands on in IP verification using System Verilog, UVM, and Verilog.
• Hands‑on experience with industry‑standard EDA tools, such as Synopsys VCS, Cadence Xcelium, or Mentor Questa, for simulation and verification.
• Strong scripting skills in Python, Perl, or Tcl for automation and efficiency in testbench development.
• Familiarity with standard protocols including JTAG, IJTAG, CRI, and APB, as well as multi‑clock domain mixed signal designs.
• Expertise in constraint‑random test generation, root cause analysis, and debugging of complex mixed signal designs.

Preferred Qualifications

• Experience with low‑power design techniques, including UPF and clock gating, to optimize power consumption.
• Knowledge of Formal Property Verification tools and version control systems such as Git or Perforce.
• Strong collaboration and communication skills with the ability to thrive in a dynamic, multi‑disciplinary team environment.

Job Type

Experienced Hire

Shift

Shift 1 (India)

Primary Location

India, Bangalore

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.