Analog Design Engineer

TylSemi, Inc.; Karnataka; On-site; INR 1,000,000 - 1,800,000; Full time

Job summary

TYLsemi is seeking an Analog Design Engineer to design high-performance analog and mixed-signal circuits for scalable AI hardware. The role spans a wide experience range (5–30 years) and requires translating system requirements into silicon-ready designs while validating performance across corners and collaborating across layout, verification, test, and product teams.

The candidate will lead the design of voltage regulators, PMICs, and power delivery blocks, leveraging Cadence Virtuoso, Spectre,

Qualifications

• Strong background in analog/mixed-signal IC design for high-current power management.
• Hands-on experience with PMIC/IVR/DC-DC regulators and switching topologies.
• Experience with 2.5D/3DIC packaging and integration with SIPI/PDN teams.

Responsibilities

• Design and deliver high-performance analog/mixed-signal circuits for robust silicon.
• Translate system requirements into silicon-ready designs and validate across corners.
• Collaborate with layout, verification, test, and product teams to ensure first-pass success.
• Lead optimization of regulators, power delivery networks and DVFS subsystems.

Skills

Analog/Mixed-signal design

High-current PMIC/IVR/DC-DC

Voltage regulator topologies

Cadence Virtuoso

MATLAB/Simulink

Education

BS/MS/PhD in Electrical Engineering (Analog & Mixed-Signal)

Tools

Cadence Virtuoso

Spectre

Clarity/EMX

MATLAB/Simulink

Job description

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

• Moore's Law is dead.2nm and beyond delivers marginal performance gains.
• Custom silicon is now mainstream.Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck.Solve hard problems and provide something which is a category in itself.

Translation:We’re entering the market at exactly the moment when every major AI/HPC player needs what we’re building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

• US team:Bay Area preferred, but we hire the best people regardless of location
• India team:Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We’re not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We’re building to win.

What We Value

• Ownership mindset.You're not here to execute someone else’s roadmap. You're here to define it.
• Bias for action.We move fast. Analysis paralysis doesn’t fly here.
• Deep technical expertise.This is hard engineering. We need people who’ve shipped real silicon and debugged real hardware.
• Low ego, high standards.We don’t care about titles or politics. We care about results.

The Ask

• The market is real.AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we’re building.
• The team has done this before.We’ve built and exited semiconductor companies at scale. This isn’t our first rodeo.
• The traction is de-risked.We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential.You’re not optimizing someone’s ad click-through rate. You’re building the silicon infrastructure that powers AI.

Here’s why you should:

• The market is real.AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we’re building.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you’re the kind of person who wants to take the shot, we’d love to talk.

READY TO JOIN?

Role Overview

As a Analog Design Engineer atTYLsemi, you will design and deliver high-performance analog and mixed-signal circuits that enable robust, manufacturable silicon. This role spans a wide experience range (5–30 years) and is ideal for engineers who combine strong fundamentals with practical execution—translating system requirements into silicon-ready designs, validating performance across corners, and partnering closely with layout, verification, test, and product teams to drive first-time-right outcomes.

WhatYou’llDo

Designof Voltage Regulatorsincludinghigh-efficiency power stages,error amplifiers, current sensing, adaptive load-line circuits, fast transient compensation,protectionand telemetry.Modeling ofmixed-signal subsystemsincludingRegulatorcontrol loops,Power delivery network, DVFS subsystemsetc.to guide architectureand designtrade-offs Lead the collaborationwith SIPI/PI, packagingteams to co-optimizeVRand power delivery.

WhatWe’reLookingFor

8+ years of hands-on analog/mixed-signal IC design experience with a strong focus on high-current, high-efficiency Power management (PMIC / IVR / DC-DC converters).Deepexpertisein different voltage regulator topologiesincluding control loopsdelivering large currentat high switching frequencies.Hands-on experience in magnetics integration for high-density IVR— including inductor modeling, coupling effects, EMI/thermal co-optimization, and 3DIC package integration.Proficiencywith industry-standarddesign and modellingtoolsincludingCadence Virtuoso,Spectre, Clarity/EMX, MATLAB/Simulink.Experience in2.5D,packagingflowsand co-design with SIPI/PDN teams.Team player with excellent communication skillsBS/ MS / PhD in Electrical Engineering (Analog & Mixed-Signal focus)

Nice to Have

Experience withstate-of-the-advantage-in AI/HPCpower delivery.Experience in designing power management switching regulators, including Buck, Boost, Buck-Boost, LDO, and other PMIC building blocks. Strong background in power management circuits such as LDOs, bandgap references, voltage/current references, protection circuits, start-up circuits, transient response optimization, and related analog power management functions.Familiarity with advanced packagingflowand thermal/PI co-optimization

Success in This Role Looks Like

Analog blocks meet spec with margin across PVT, mismatch, and post-layout effectsDesign reviews are crisp: requirements, tradeoffs, and risks are clearly articulated and managedSiliconbring-up converges quickly through strong correlation, structured debug, and decisive fixesCross-functional partners (layout, verification, test, validation) can execute efficiently with clear interfaces and documentation Reusable design collateral and improvedmethodologyreduce cycle time and increase first-pass success