RTL Design Engineer

TYLsemi; India; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

TylSemi Solutions Private Limited in India is seeking an RTL Design Engineer to design high-performance digital IPs and SoC components for AI, HPC, and Networking applications.

You will work with architecture, verification, physical design and software teams to deliver silicon solutions, optimize timing, area and power, and contribute to design reviews and integration efforts.

Qualifications

• Bachelor's or master's degree in electrical engineering, electronics engineering, computer engineering or a related field.
• 5+ years of RTL design and digital IC development.
• Strong fundamentals in digital design, computer architecture, and ASIC flow.
• Proficiency in Verilog/SystemVerilog, RTL coding, FSMs, CDC and low-power design.
• Experience with simulation and debugging tools; familiarity with synthesis and timing analysis.

Responsibilities

• Develop RTL designs using Verilog/SystemVerilog based on architecture specifications.
• Participate in microarchitecture definition and design reviews.
• Implement high-performance, area-efficient, and power-optimized digital logic.
• Develop and maintain design documentation, specifications, and implementation guidelines.
• Collaborate with verification engineers to define verification strategies and debug issues.
• Perform RTL simulations and support design validation activities.
• Analyze synthesis results and work with physical design teams to optimize timing, power and area.
• Support SoC integration activities and resolve integration-related issues.
• Participate in design reviews, code reviews, and quality improvement initiatives.
• Work with cross-functional teams throughout the ASIC development lifecycle.

Skills

Verilog/SystemVerilog

RTL design

FSMs

CDC

Low-power design

Simulation

Timing analysis

Analytical thinking

Education

Bachelor's/Master's in EE/EC/CS

Tools

FPGA prototyping

Job description

Role Overview

TylSemi Solutions Private Limited is seeking a talented and motivated RTL Design Engineer to join our growing semiconductor design team. In this role, you will be responsible for the design and development of high-performance digital IPs and SoC components for next-generation AI, HPC, and Networking applications. You will work closely with architecture, verification, physical design, and software teams to deliver robust and scalable silicon solutions.

What You'll Do

• Develop RTL designs using Verilog/System Verilog based on architectural and microarchitecture specifications.
• Participate in microarchitecture definition and design reviews.
• Implement high-performance, area-efficient, and power-optimized digital logic.
• Develop and maintain design documentation, specifications, and implementation guidelines.
• Collaborate with verification engineers to define verification strategies and debug functional issues.
• Perform RTL simulations and support design validation activities.
• Analyze synthesis results and work with physical design teams to optimize timing, power, and area.
• Support SoC integration activities and resolve integration-related issues.
• Participate in design reviews, code reviews, and quality improvement initiatives.
• Work closely with cross-functional teams throughout the ASIC development lifecycle.

Required Qualifications

• Bachelor's or master's degree in electrical engineering, Electronics Engineering, Computer Engineering, or related field.
• 5+years experience in RTL design and digital IC development.
• Strong understanding of digital design fundamentals, computer architecture, and ASIC design flow.
• Proficiency in:
  • Verilog/System Verilog
  • RTL design and coding methodologies
  • Logic design and finite state machines (FSMs)
  • Clock domain crossing (CDC) concepts
  • Low-power design fundamentals
• Experience with simulation and debugging tools.
• Familiarity with synthesis and timing analysis concepts.
• Strong analytical and problem-solving skills.

Preferred Qualifications

• Experience designing IPs or subsystems for AI, HPC, Networking, or data-center applications.
• Knowledge of industry-standard protocols such as:
  • AXI/AHB/APB
  • PCIe
  • DDR
  • Ethernet
  • CXL
  • UCIe
• Familiarity with scripting languages such as Python, Perl, Shell, or TCL.
• Exposure to low-power design methodologies and power intent formats (UPF/CPF).
• Understanding of linting, CDC, RDC, and formal verification tools.
• Experience with FPGA prototyping is a plus.

Key Attributes

• Strong attention to detail and commitment to design quality.
• Passion for semiconductor innovation and cutting-edge technologies.
• Excellent debugging and problem-solving abilities.

  About TylSemi, Inc.

  The Opportunity

  The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package? That's what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

  This isn't a nice-to-have. It's the critical path.

  Why Now

  The Market Window

  • Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
  • Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
  • IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

  Translation:

  We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

  Culture & Team: How We Work

  No Politics, No Bureaucracy. There are no layers, no approval chains, no corporate theater.

  • If you have an idea, we test it. If it works, we ship it.
  • No endless meetings, no PowerPoint presentations to convince middle management.

  Remote-Friendly, Global Team

  • US team: Bay Area preferred, but we hire the best people regardless of location
  • India team: Building a world-class design center in Bangalore

  Move Fast, Ship Real Products

  We're not a research project. We have paying customers, committed capital, and aggressive timelines. This is a company, not a lifestyle business. We're building to win.

  What We Value

  • Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
  • Bias for action. We move fast. Analysis paralysis doesn't fly here.
  • Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
  • Low ego, high standards. We don't care about titles or politics. We care about results.

  The Ask

  If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits. We’re asking you to walk away from that and bet on us.

  Here’s Why You Should

  • The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
  • The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
  • The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
  • The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

  Or stay comfortable. No judgment. But if you're the kind of person who wants to take the shot, we'd love to talk.

  READY TO JOIN?