Memory Systems Performance & Workload Architect - SMTS

Micron Technology, Inc; Bengaluru; On-site; INR 3,000,000 - 7,000,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid family leave

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks a Memory Systems Performance & Workload Architect (SMTS/DMTS) to lead workload-driven memory architecture and performance strategy across mobile and server platforms. You will own workload characterization, benchmarking, and performance modeling to shape DRAM, LPDDR, and HBM based systems.

Expect cross-functional collaboration with silicon, controllers, firmware, OS, and hyperscalers. Role type is DMTS/SMTS.

Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, or related field with 15+ years of experience, OR
• Master's degree with 14+ years of experience, OR
• PhD with 12+ years of experience.

Responsibilities

• Define the benchmarking framework for Mobile and Server workloads.
• Characterize memory bandwidth, latency, QoS, tail latency, and NUMA behavior at scale.
• Lead deep dives using perf, eBPF, and PMU-based profiling to identify bottlenecks.
• Drive system-level optimizations across OS, firmware and hardware.

Skills

Python

C/C++

Linux perf tools

eBPF

PMU profiling

Education

Bachelor's degree in Computer Science/Electrical Engineering

Master's degree

PhD

Tools

SPEC

MLPerf

STREAM

Linux perf

Job description

JR102526 Memory Systems Performance & Workload Architect - SMTS

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Lead Micron's workload-driven memory architecture and performance strategy across mobile and server-class platforms, shaping the future of DRAM, LPDDR, and HBM based memory systems. Own the end-to-end vision for workload characterization, benchmarking, and performance modeling, translating real-world application behavior into next-generation memory architecture, product features, and ecosystem innovations. Drive cross-organizational alignment spanning silicon, controllers, firmware, OS, hyperscalers, and industry partners, establishing Micron as a leader in workload-informed memory design.

Role Type: DMTS/SMTS

Domain: Memory Systems Architecture, Workload Analysis, Performance Engineering for servers and mobiles.

Key Responsibilities

Benchmarking & Workload Characterization

• Define the industry-leading benchmarking framework for Mobile(Geekbench, PCMark, MLPerf Mobile, real app traces etc) and Server( SPEC CPU, SPECrate, STREAM, MLPerf, database/cloud workloads)
• Characterize, Memory bandwidth, latency, QoS, tail latency, Access patterns (locality, working set, read/write mix), NUMA behavior, cache interaction, memory-level parallelism
• Define and maintain representative workload suites for customer scenarios

Root Cause Analysis & Optimization

• Lead deep dives using PMU counters, perf, eBPF, ftrace, ARM Streamline / VTune equivalents
• Identify bottlenecks in Memory controller scheduling, DRAM timing and row-buffer locality, Cache/memory interaction
• Drive optimizations across, Kernel (NUMA, huge pages, memory policies), Firmware / BIOS tuning, Application-level performance tuning

Architecture & System-Level Innovation

• Drive system-level tradeoff analysis (performance, power, cost, scalability) to guide product decisions.
• Influence memory controller policies (scheduling, QoS, fairness) and the evolution of heterogeneous/tiered memory hierarchies.

Modeling & Predictive Analytics

• Establish advanced frameworks for performance modeling, analytical simulation, and trace-driven workload replay at scale.
• Lead what-if exploration for future workloads (AI-first systems) and scaling across memory configurations (channels, ranks, interleaving, bandwidth).
• Translate models into product requirements, performance targets, and customer-facing guidance.

Cross-Stack Optimization

• Drive end-to-end optimizations across application > OS > firmware > hardware stack.
• Influence Linux kernel memory management (NUMA, huge pages, scheduling), data placement, and memory tiering strategies.
• Partner with ecosystem teams to optimize AI frameworks, databases, and virtualization platforms for memory efficiency and performance.

Minimum Qualifications

• 15-24+ years in memory systems, performance engineering, or system architecture.
• Proven expertise in workload analysis and workload characterization at scale for servers and mobiles.
• Strong programming experience: Python, C/C++, and system-level tooling.
• Deep experience with benchmarking suites (SPEC, MLPerf, STREAM, and real-world workloads) and Linux performance tools (perf, eBPF, PMU-based profiling).
• Demonstrated impact on architecture decisions and product roadmaps through cross-functional leadership.

Ideal Attributes

• Visionary thinker who connects workload trends > architecture > product strategy.
• Strong analytical, modeling, and data-driven decision-making capability.
• Exceptional ability to influence at executive and cross-organizational levels.
• Track record of industry impact (ecosystem leadership, standards, publications, or open source).
• Passion for innovation in next-generation memory systems.

Basic Qualifications

• Bachelor's degree in Computer Science, Electrical Engineering, or related field with 15+ years of experience, OR
• Master's degree with 14+ years of experience, OR
• PhD with 12+ years of experience.
• 5+ years of experience with programming languages such as Python, C, C++, or Java.

Preferred Skills

• Experience with AI/ML workloads (LLMs, recommendation systems, training clusters) and performance optimization.
• Expertise in databases and cloud-native systems (RocksDB, MySQL/PostgreSQL, Redis/Memcached) and microservices.
• Expertise in performance modeling, simulation, and trace-driven workload replay frameworks.
• Familiarity with ARM and x86 system architectures and performance tooling.

Job Profile(s): Systems Design Engineering SMTS

Relocation level: (TBD)

Before Getting Started

• Hiring managers may view your performance appraisals, original resume, transcripts or other performance-related documentation in your personal file. This information will be held in confidence.
• If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.