Memory Systems Performance & Workload Architect - SMTS

Micron Technology; Bengaluru; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

Micron Technology in Bengaluru is seeking a DMTS/SMTS specializing in Memory Systems Architecture and Performance Engineering. The ideal candidate will have 15-24+ years of experience in memory systems and performance engineering, with expertise in workload characterization for servers and mobiles.

Candidates should be adept in Python and C/C++ programming and demonstrate leadership in architecture decisions. Responsibilities include defining benchmarking frameworks and driving optimizations across various system components.

Qualifications

• 15–24+ years in memory systems, performance engineering, or system architecture.
• Strong programming experience in Python, C/C++, and system-level tooling.
• Deep experience with benchmarking suites and Linux performance tools.

Responsibilities

• Define the industry-leading benchmarking framework for Mobile and Server.
• Lead deep dives using PMU counters and identify bottlenecks.
• Drive system-level tradeoff analysis to guide product decisions.
• Establish frameworks for performance modeling and analytics.
• Drive optimizations across the application, OS, firmware, and hardware stack.

Skills

Workload analysis

Python

C/C++

System-level tooling

Performance engineering

Education

Bachelor’s degree in Computer Science or Electrical Engineering

Master’s degree

PhD

Tools

SPEC

MLPerf

STREAM

Linux performance tools

Job description

Our vision is to transform how the world uses information to enrich life for all.

Role Type

DMTS/SMTS

Domain

Memory Systems Architecture, Workload Analysis, Performance Engineering for servers and mobiles

Key Responsibilities

• Benchmarking & Workload Characterization: Define the industry-leading benchmarking framework for Mobile (Geekbench, PCMark, MLPerf Mobile, real app traces) and Server (SPECCPU, SPECrate, STREAM, MLPerf, database/cloud workloads); characterize memory bandwidth, latency, QoS, tail latency, access patterns (locality, working set, read/write mix), NUMA behavior, cache interaction, memory-level parallelism; define and maintain representative workload suites for customer scenarios.
• Root Cause Analysis & Optimization: Lead deep dives using PMU counters, perf, eBPF, ftrace, ARM Streamline / VTune equivalents; identify bottlenecks in memory controller scheduling, DRAM timing and row-buffer locality, cache/memory interaction; drive optimizations across kernel (NUMA, huge pages, memory policies), firmware/BIOS tuning, application-level performance tuning.
• Architecture & System-Level Innovation: Drive system-level tradeoff analysis (performance, power, cost, scalability) to guide product decisions; influence memory controller policies (scheduling, QoS, fairness) and the evolution of heterogeneous/tiered memory hierarchies.
• Modeling & Predictive Analytics: Establish advanced frameworks for performance modeling, analytical simulation, and trace-driven workload replay at scale; lead what-if exploration for future workloads (AI-first systems) and scaling across memory configurations (channels, ranks, interleaving, bandwidth); translate models into product requirements, performance targets, and customer-facing guidance.
• Cross-Stack Optimization: Drive end-to-end optimizations across application → OS → firmware → hardware stack; influence Linux kernel memory management (NUMA, huge pages, scheduling), data placement, and memory tiering strategies; partner with ecosystem teams to optimize AI frameworks, databases, and virtualization platforms for memory efficiency and performance.

Minimum Qualifications

• 15–24+ years in memory systems, performance engineering, or system architecture.
• Proven expertise in workload analysis and workload characterization at scale for servers and mobiles.
• Strong programming experience: Python, C/C++, and system-level tooling.
• Deep experience with benchmarking suites (SPEC, MLPerf, STREAM, and real-world workloads) and Linux performance tools (perf, eBPF, PMU-based profiling).
• Demonstrated impact on architecture decisions and product roadmaps through cross-functional leadership.

Ideal Attributes

• Visionary thinker who connects workload trends → architecture → product strategy.
• Strong analytical, modeling, and data-driven decision-making capability.
• Exceptional ability to influence at executive and cross-organizational levels.
• Track record of industry impact (ecosystem leadership, standards, publications, or open source).
• Passion for innovation in next-generation memory systems.

Basic Qualifications

• Bachelor’s degree in Computer Science, Electrical Engineering, or related field with 15+ years of experience, OR
• Master’s degree with 14+ years of experience, OR
• PhD with 12+ years of experience.
• 5+ years of experience with programming languages such as Python, C, C++, or Java.

Preferred Skills

• Experience with AI/ML workloads (LLMs, recommendation systems, training clusters) and performance optimization.
• Expertise in databases and cloud-native systems (RocksDB, MySQL/PostgreSQL, Redis/Memcached) and microservices.
• Expertise in performance modeling, simulation, and trace-driven workload replay frameworks.
• Familiarity with ARM and x86 system architectures and performance tooling.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.