System Architect – Advanced Memory System Architecture

Jobtailor; Bengaluru; On-site; INR 1,200,000 - 2,500,000; Full time

Job summary

Jobtailor seeks a memory architecture engineer to optimize next-generation memory and storage subsystems. You will work with design and system teams to identify bottlenecks and propose novel solutions, and you will perform system-level simulations to compare architectures.

The role requires strong C/C++ skills, with Python and SystemC as a plus, and deep knowledge of DDR/NVDIMM memory systems and STL usage. You will be a key contributor in a highly collaborative environment.

Qualifications

• Experience in computer architecture analysis and design tradeoffs.
• Experience with large-scale server systems focusing on memory and storage subsystems.
• C/C++ programming experience; Python and SystemC are a plus.
• Familiarity with the C++ STL.
• Knowledge of memory controller architectures, DDR, NVDIMM.
• Strong problem solving and communication skills; well organized.

Responsibilities

• Deliver architectures and innovative solutions to optimize power and performance of memory and storage subsystems.
• Collaborate with design and system teams to identify requirements and bottlenecks.
• Perform system-level simulations comparing new architectures with existing ones.
• Develop models of controllers, memory devices, interconnects, and processors.
• Benchmark and analyze memory/storage access patterns.
• Model and analyze innovations to demonstrate benefits and tradeoffs.

Skills

C/C++ programming

Python

SystemC

STL

Memory architecture

DDR/NVDIMM knowledge

Architecture tradeoff analysis

OS memory management

Tools

Modeling tools

Job description

Responsibilities

• Delivering architectures and innovative solutions to optimize power and performance of next‑generation memory and storage subsystems.
• Working with design and system architecture teams to identify key system requirements, seek the current bottlenecks and propose novel solutions for a wide range of applications.
• Performing system‑level simulations of innovative architectures to compare with existing design paradigms, using both open and closed‑loop system performance analysis.
• Developing models of new controllers, components, memory devices, interconnects, and processors.
• Capturing, benchmarking, analyzing applications and their corresponding memory and storage access patterns.
• Crafting innovative solutions, modeling, and analyzing them to demonstrate their benefits and tradeoffs.

Requirements

• Must have strong exposure to computer architecture analysis and design tradeoffs.
• Must have exposure to large scale server systems with an emphasis on memory and storage subsystems.
• Must have exposure to architectures for large, sophisticated blocks and measuring their impact at the system‑level.
• Must have C/C++ experience; Python and SystemC experience is a plus.
• Must understand how to use the C++ Standard Template Library (STL).
• Experience in memory and storage controller architecture, protocols, DDR, NVDIMM, is a plus.
• Deep knowledge of architecture tradeoff analysis and modeling tools and methodologies.
• Exposure to software development practices.
• A strong knowledge through academic coursework or experience in DRAM and NAND memory systems is preferred.
• Exposure to operating system (OS) memory management is a plus.
• Ability to quickly react and adapt to changes based on modeling results, or project changes.
• Excellent problem solving and troubleshooting skills.
• Excellent verbal communication and written skills.
• Must be highly organized and self‑motivated.
• Must be a strong individual contributor as well as a team player.

Core Competencies

Demonstrates expertise in computer architecture analysis, memory and storage subsystem optimization, and system‑level performance evaluation. Proficient in C/C++ programming and familiar with modeling tools and methodologies for architecture tradeoff analysis.