Memory Layout Manager

Intel Corporation; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Intel Corporation in Bengaluru seeks an experienced Layout Design Engineering Manager to lead a team of layout engineers, delivering SRAM, RF, ROM, and CAM memory compiler designs on FinFET/GAA technologies. You will guide technical execution, optimize floorplanning, placement, routing, and sign-off processes, and drive innovation with AI-driven automation.

The role requires 15+ years in memory layout design, tape-out success on cutting-edge nodes, and strong leadership.

Qualifications

• Minimum 15+ years of deep technical experience in memory compiler layout design and management.
• Proven track record of successful tape-outs on cutting-edge foundry geometries (3nm/2nm) using Cadence Virtuoso, Calibre, and IC Validator.
• Demonstrated ability to lead teams and manage complex projects in a fast-paced semiconductor environment.
• Strong interpersonal communication and leadership skills; capable of scaling high-performing teams.

Responsibilities

• Lead and mentor a team of layout design engineers to deliver world-class memory compiler designs on FinFET/GAA technologies.
• Oversee design, development, modification, analysis, and verification of memory compiler layouts.
• Provide technical guidance for analog, digital, memory, and standard-cell layouts and flows.
• Enable teams to automate repetitive tasks using AI-driven EDA tools and custom flows.
• Drive team results by fostering a culture of innovation and accountability.
• Manage resources effectively to meet performance targets and timelines.

Skills

Leadership

Cross-functional collaboration

Mentoring

AI/ML in EDA

Problem solving

Education

Bachelor’s or Master’s in Electronics/Electrical/VLSI Engineering

Tools

Cadence Virtuoso

Siemens Calibre

Synopsys IC Validator

Job description

Job Details:

Job Description:

The Role and Impact We are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel’s bleeding FinFETs,GAA technologies. In this role, you will champion technical execution by overseeing compiler friendly and optimized floorplanning, high-density,performance based placement and routing template, and rigorous physical sign-off processes including DRC, LVS, Yield, DFM, Density, parasitic extraction, Noise Reliability i.e. EM, IR. You will provide technical guidance, set clear goals, and foster cross-functional collaboration with circuit design, Tilers, and foundry teams to meticulously optimize memory area, performance, power, and yield. Beyond daily execution, you will spearhead layout methodology innovations, establish advanced automation flows using SKILL, Python, or Tcl, and cultivate a culture of technical excellence by mentoring senior and staff-level engineers. The role requires a strong vision for leveraging AI and ML technologies (such as reinforcement learning for routing or predictive analytics for DRC debugging) to make execution significantly more efficient, robust, and high-quality.

• Lead and mentor a team of layout design engineers to developed world class memory compiler designs on FinFets/GAA technologies, ensuring alignment with organizational goals and timelines.
• Oversee the design, development, modification, analysis, and verification of memory compiler layout designs.
• Provide technical guidance for analog, digital, memory, and standard cell layout methodologies, compilers, tools, and flows.
• Enable teams to execute effectively by setting clear objectives, maintaining accountability and facilitating productive workflows through AI-driven EDA tools and generative machine learning models into the design lifecycle to automate repetitive layout tasks, accelerate routing, and optimize cell placement.
• Drive team results by inspiring and developing team members, modeling Intel values, and fostering a supportive and collaborative environment.
• Manage resources effectively to optimize project execution and meet performance targets.

Qualifications:

• Minimum Qualifications - Candidates must possess a Bachelor’s or Master’s degree in Electronics, Electrical, or VLSI Engineering paired with 15+ years of deep technical experience in memory compiler layout design and management.
• You must have a proven track record of successful tape-outs on cutting-edge foundry geometries (such as 3nm, 2nm, or below) using industry-standard EDA environments like Cadence Virtuoso, Siemens Calibre, and Synopsys IC Validator along with expert-level proficiency in driving layout methodologies and flows for analog, digital, memory, and standard cells.
• Demonstrated ability to lead teams and manage complex projects effectively.
• Demonstration of strong emotional intelligence, exceptional interpersonal communication, and an ability to lead, scaling high-performing engineering teams in a fast-paced semiconductor environment.
• Preferred Qualifications - Strong communication and interpersonal skills with the ability to collaborate across teams and disciplines.
• Experience in strategic decision-making and performance management for technical teams.
• A track record of fostering innovation and driving a culture of excellence.
• Passion for developing team members and maintaining a productive and inclusive work environment.

Join us in shaping the future of technology and take your leadership and technical expertise to the next level by driving meaningful innovation at Intel.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.