Memory Layout Engineer

Dignifyd; Bengaluru; On-site; INR 900,000 - 1,500,000; Full time

Job summary

Dignifyd in Bengaluru is seeking an experienced Memory Layout Engineer with 3+ years of hands-on design and physical layout skills. You will develop memory layout schemes, implement layouts, and ensure verification against design rules for advanced nodes.

You will collaborate with circuit, physical design, and verification teams to optimize layouts and resolve DRC/LVS issues, supporting technology nodes from TSMC and/or Samsung.

Qualifications

• Minimum 3+ years of experience in Memory Layout Design.
• Exposure to advanced semiconductor tech nodes.
• Experience with TSMC and/or Samsung process technologies.
• Understanding of memory layout implementation and physical verification.

Responsibilities

• Develop and implement memory layout designs based on design specifications.
• Work on memory layout implementation, optimization, and physical verification.
• Ensure layout quality, design accuracy, and compliance with foundry requirements.
• Collaborate with circuit design, physical design, and verification teams.
• Perform layout-related checks and resolve DRC violations.
• Support layout optimization for advanced technology nodes.

Skills

Memory Layout Design

Physical Layout

DRC/LVS

Semiconductor Nodes

Process Technologies

Job description

We are looking for an experienced Memory Layout Engineer with a minimum of 3+ years of hands‑on experience in Memory Layout Design and Physical Layout implementation. The candidate should have exposure to advanced semiconductor technology nodes, particularly TSMC and/or Samsung process technologies.

Key Responsibilities

• Develop and implement memory layout designs based on design specifications.
• Work on memory layout implementation, optimization, and physical verification.
• Ensure layout quality, design accuracy, and compliance with foundry requirements.
• Collaborate with circuit design, physical design, and verification teams.
• Perform layout-related checks and resolve Design Rule Check (DRC) violations.
• Support layout optimization for advanced technology nodes.

Required Skills & Technical Expertise

• Minimum 3+ years of experience in Memory Layout Design.
• Hands‑on experience with advanced semiconductor technology nodes.
• Experience with TSMC and/or Samsung process technologies.
• Understanding of memory layout implementation and physical verification.
• Knowledge of DRC, LVS, and other physical verification concepts is preferred.