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LeadSOC Technologies Pvt Ltd is seeking a Memory Layout Engineer with 3+ years of hands-on experience in custom memory circuit layout, verification, and semiconductor design methodologies. The role focuses on SRAM/DRAM layout, layout verification, and integration with standard cell libraries in FinFET process nodes.
The successful candidate will work with Cadence Virtuoso and physical verification tools like Calibre, contribute to memory architecture and peripheral circuits, and demonstrate
Experience: 3+ Years
Job Title: Memory Layout Engineer
Employment Type: Full-time
We are looking for a skilled Memory Layout Engineer with 3+ years of experience in custom layout design and implementation of memory circuits. The candidate should have strong knowledge of SRAM/DRAM layout, layout verification, physical verification, and semiconductor design methodologies.