Memory layou

Acldigital; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

ACL Digital in Bengaluru seeks an expert SRAM layout engineer to design leaf cell layouts and contribute to SRAM compiler development. You will independently drive LVS and DRC verification and closure, and optimize memory layout strategies to meet area, performance, and power goals.

You should bring strong debugging abilities, a solid understanding of physical design flows, and a proven track record in memory layout methodologies, verification flows, and problem solving in complex silicon

Qualifications

• Strong expertise in SRAM layout design and compiler development.
• Capable of independently handling LVS/DRC verification and closure.
• Good understanding of memory layout optimization techniques.
• Strong problem-solving and debugging skills in physical design environments.

Responsibilities

• Design and develop SRAM leaf cell layouts.
• Work on SRAM compiler layout development and enhancements.

Skills

SRAM layout

Compiler development

LVS/DRC verification

Memory optimization

Debugging skills

Job description

Expertise in SRAM leaf cell layout development

EM/IR analysis and fixing experience

Ability to independently perform LVS and DRC closure at compilerlevel

Good understanding of memory layout methodologies and physical verificationflows

IDEAL CANDIDATE

• Strong expertise in SRAM layout design and compiler development


• Capable of independently handling LVS/DRC verification and closure


• Good understanding of memory layout optimization techniques


• Strong problem-solving and debugging skills in physical design environments

WHAT THE ROLE INVOLVES

• Design and develop SRAM leaf cell layouts


• Work on SRAM compiler layout development and enhancements