Sr. Memory Layout Design Engineer

Broadcom, Inc.; Bengaluru; On-site; INR 3,500,000 - 7,000,000; Full time

Job summary

Broadcom, Inc. in Bengaluru is seeking a Sr. Memory Layout Design Engineer to drive end-to-end memory layout and integration for advanced CMOS processes.

You will apply layout guidelines, ensure timing and power planning, and collaborate with SOC teams to deliver quality silicon on schedule. The role requires 8+ years in memory layout, strong Cadence tools experience (Virtuoso XL, VXL/EXL), and a proven track record in memory architecture, RC management, and physical verification.

Qualifications

• Minimum 8 years of experience in memory layout design and physical verification.
• Proficiency in Cadence layout tools and CALIBRE verification.
• Strong knowledge of memory architecture and RC planning.
• Experience with memory integration and floor-planning.

Responsibilities

• Understand and apply layout guidelines and process rules for quality layouts.
• Manage scheduling, timelines, and layout floor-planning.
• Deliver start-to-end layout deliverables within the project schedule.
• Adapt to new methodologies and communicate with SOC/library teams.
• Lead layout scripting and automation initiatives.

Skills

Memory layout design

Physical verification

Cadence tools

CALIBRE verification

Floor planning

Chip integration

Scripting & SKILL

Team leadership

Education

Bachelor's degree

Tools

Cadence Virtuoso XL

VXL

EXL

Job description

Sr. Memory Layout Design Engineer### Sr. Memory Layout Design EngineerApply: IND-Bangalore Electronic City - S1: Full time: Posted Yesterday: R027716**Please Note:****1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)****2. If you already have a Candidate Account, please Sign-In before you apply.**## **Job Description:****Job Requirements:**- Minimum 8 years of experience with strong layout knowledge- Bachelor's degree required.- Proficiency in using Cadence tools (virtuotso layout, layotu XL, Cadence schematic capture, and verification tools - CALIBRE & Hercules).- Strong layout knowledge in submicron processes (e.g. 7nm, 5nm, 3nm, 2nm).- Experience in digital layout (Standard cell, Memory, I/O); analog layout experience is a plus.**Job Description:**- Understand and apply layout guidelines, new process rules, and technical requirements for good quality layout.- Manage scheduling, timelines, and layout floor-planning.- Responsible for start to end deliverables with quality within the planned schedule.- Adapt quickly to new methodologies, remain open to new ideas, and communicate effectively with the SOC/library team.- Able to think and help in layout scripting and automation**Skill Set (Memory):**- Strong experience in Memory layout design and physical verification (LVS, DRC, ERC, Antenna, ElectroMigration) in CMOS processes.- Experience with Cadence Layout tools (VIRTUOSO XL, VXL, or EXL) and CALIBRE verification tools.- Proficiency in floor-planning, hierarchy layout, and chip integration.- Understanding of memory architecture, RC requirement, ability to plan signal and power, based on the layout guidelines- Knowledge of AI, automation in layout, Script Programming and SKILL Programming- Ability to lead, train junior engineers, and manage projects effectively.- Good knowledge of memory layout topology; experience with memory compilers is a plus.- Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.- Self-reliant with the ability to work both independently and collaboratively.**Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.****If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.**