Lead/Staff Engineer – Synthesizable IP Design, Emulation & FPGA Prototyping

Qualcomm; Bengaluru; On-site; INR 3,000,000 - 6,000,000; Full time

Job summary

Qualcomm India Private Limited seeks an experienced Lead/Staff Engineer with 5+ years in ASIC/SoC design to lead synthesizable IP model development for emulation and FPGA prototyping. You will contribute to architecture, drive execution, and provide technical leadership across multidisciplinary teams.

The role requires strong RTL/C++ modeling, FPGA implementation, hardware emulation experience, and collaboration with architecture, verification, software, and system teams to enable platform

Qualifications

• Bachelors degree in Electrical, Electronics, CS, or related field and 4+ years Hardware Engineering or related work experience.
• Masters degree in Electrical, Electronics, CS, or related field and 3+ years Hardware Engineering or related work experience.
• PhD in Electrical/ Electronics, CS, or related field and 2+ years Hardware Engineering or related work experience.

Responsibilities

• Lead the design and development of synthesizable IP models for emulation and FPGA prototyping platforms.
• Contribute to architecture and micro-architecture definition, design reviews, and implementation strategies.
• Develop and optimize Verilog/SystemVerilog RTL for functionality, performance, area, and timing.
• Develop and maintain C/C++ reference models and ensure functional alignment between software models and RTL.
• Drive IP integration, debug, validation, and bring-up across simulation, emulation, and FPGA environments.
• Support FPGA synthesis, implementation, timing closure, hardware validation, and performance optimization.
• Collaborate with architecture, verification, software, and system teams to enable platform bring-up and software development.
• Own project planning, technical risk assessment, schedule estimation, and execution against committed milestones.
• Drive productivity improvements through automation and AI-assisted design methodologies.

Skills

Verilog/SystemVerilog RTL

C/C++

Architecture/micro-architecture

Debugging RTL/FPGA/system-level issues

Git/CI/CD, scripting (Python, Tcl, etc

Education

Bachelor's degree in Electrical/ Electronics/ CS/ related

Master's degree in Electrical/ Electronics/ CS/ related

PhD in relevant field

Tools

Vivado

Veloce/ZeBu/Cadence Emulation

Palladium

HDL simulators

Job description

Company: Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

We are seeking an experienced Lead/Staff Engineer with 5 + years of ASIC/SoC design experience to lead the development and delivery of synthesizable IP models for advanced emulation and FPGA prototyping platforms.

The ideal candidate will bring strong expertise in RTL design, C/C++ modeling, FPGA implementation, and hardware emulation, along with the ability to contribute to architecture, drive complex technical execution, and provide technical leadership across multidisciplinary teams.

Key Responsibilities

• Lead the design and development of synthesizable IP models for emulation and FPGA prototyping platforms.
• Contribute to architecture and micro-architecture definition, design reviews, and implementation strategies.
• Develop and optimize Verilog/SystemVerilog RTL for functionality, performance, area, and timing.
• Develop and maintain C/C++ reference models and ensure functional alignment between software models and RTL.
• Drive IP integration, debug, validation, and bring-up across simulation, emulation, and FPGA environments.
• Support FPGA synthesis, implementation, timing closure, hardware validation, and performance optimization.
• Collaborate with architecture, verification, software, and system teams to enable platform bring-up and software development.
• Own project planning, technical risk assessment, schedule estimation, and execution against committed milestones.
• Drive productivity improvements through automation and AI-assisted design methodologies.

Required Qualifications

• Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or a related discipline.
• 5+ years of experience in ASIC/SoC/FPGA design, RTL development, emulation, or prototyping.
• Proven experience delivering complex IP, subsystem, or SoC designs through development, integration, and validation.
• Strong experience in synthesizable RTL/IP model development and ASIC/SoC design methodologies.

Technical Expertise

• Strong hands-on expertise in Verilog/SystemVerilog RTL design and synthesizable model development.
• Ability to translate architecture and micro-architecture specifications into high-quality, implementation-ready RTL.
• Strong C/C++ programming skills with experience developing reference models and validation frameworks.
• Good understanding of CDC, reset architecture, power management, and system-level integration.
• Familiarity with bus/interconnect protocols such as AXI, AHB, and APB.
• Experience with Git, CI/CD workflows, and scripting using Python, Tcl, Perl, or Shell.

Emulation & FPGA Prototyping

• Hands-on experience with AMD/Xilinx FPGA design and prototyping flows, including UltraScale+ and Versal architectures.
• Experience with Vivado, including FPGA synthesis, implementation, timing closure, debug, and hardware bring-up.
• Familiarity with emulation platforms such as Siemens Veloce/Veloce TBX, Cadence ZeBu, Palladium, or equivalent technologies.
• Understanding of SCE-MI, DPI-C, transactors, transaction-based acceleration, co-emulation, and software-driven validation.
• Experience with multi-FPGA partitioning and system-level integration is highly desirable.

Protocol Expertise

Experience or familiarity with one or more of the following:

• LPDDR5/LPDDR5X/LPDDR6, PCIe, Ethernet, USB, UART, I2C/I3C, MIPI C-PHY/D-PHY, AXI, AHB, and APB.

Preferred Qualifications

• Experience with large-scale SoC prototyping, emulation-based validation, and software bring-up.
• Experience with multi-FPGA prototyping and partitioning.
• Exposure to HLS methodologies and cloud-based EDA workflows.
• Familiarity with AI-assisted semiconductor design methodologies, Generative AI, automation frameworks, and engineering productivity tools.

Leadership & Collaboration

• Strong analytical and problem-solving skills with the ability to debug complex RTL, FPGA, and system-level issues.
• Ability to lead technical discussions and influence architecture and implementation decisions.
• Experience mentoring engineers and driving engineering best practices and design quality.
• Strong project ownership with the ability to plan, prioritize, identify risks, and execute independently.
• Excellent communication and cross-functional collaboration skills.
• Strong focus on engineering excellence, innovation, execution, and continuous improvement.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
• Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
• PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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