Lead Product Engineer

Cadence; Pune District; On-site; INR 1,800,000 - 2,400,000; Full time

Job summary

Cadence seeks a Product Engineer Memory IP Products to join our memory IP team. You will help drive pre-sales and post-sales support for DDR/LPDDR/HBM/GDDR memory IP and collaborate with global teams to deliver high-performance solutions.

You will interface with customers, R&D, and System Validation, tackle complex issues, participate in design reviews, and contribute to product documentation while leveraging AI tools to improve productivity.

Qualifications

• B.S Electrical/Computer Engineering or similar required.
• 4+ years of experience in memory IP / DDR/LPDDR/HBM/IPs.
• Verilog RTL design and gate-level verification experience.
• Familiarity with DFT flows and timing analysis.

Responsibilities

• Supporting pre-silicon integration, usage, and implementation of memory subsystem products.
• Analyzing and resolving complex subsystem issues and guiding customers.
• Participating in memory PHY/Controller IP reviews and integration discussions.
• Assisting customers with RTL/gate-level simulations and timing closure.
• Contributing to product documentation and customer checklists.

Skills

Verilog RTL design

Gate-level verification

Pre-silicon integration

Excellent communication

Education

B.S Electrical/Computer Engineering

M.S Electrical/Computer Engineering

Tools

Synthesis tools

Static timing analysis

DFT flows

Board/packaging design

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Product Engineer Memory IP Products

Join a growing and dynamic IP team and help lead the proliferation of best-in-class Memory PHY IP products across a wider range of customers. This is a tremendous opportunity to work with an experienced team focusing on development and support of high-performance IP related to memory protocols such as DDR/LPDDR/HBM/GDDR, and to engage with the technology sector s top companies making an impact in our world.

The role will be a key member of technical staff in an organization responsible for activities including but not limited to pre-sales engagement with potential customers and post-sales technical support for integration, usage, and deployment of memory physical IP producs. This candidate will be the primary interface between customers, CDNS R&D and System Validation teams. Candidate should possess strong communication skills with ability to manage multiple priorities on a day-to-day basis. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear oral and written communication skills are must-have attributes in this role.

Primary Responsibilities:

• Supporting pre-silicon integration, usage, and implementation of memory subsystem products
• Helping with internal system integration and QA testing of memory subsystem products (Controller + PHY)
• Analyzing and resolving complex subsystem application or implementation issues and providing professional guidance to customers
• Supporting various memory PHY and controller SOC integration reviews and implementation reviews
• Assisting customers with RTL and gate-level simulations to verify functionality
• Assisting customers with timing closure and other aspects of physical integration
• Participating in development and refinement of product documentation and checklists for customer applications
• Supporting post-silicon bringup and production test activities for customers as needed
• Enhancing customer experience by providing prompt, thorough, and technically accurate responses to customer questions
• Leveraging AI-powered tools and assistants to enhance productivity, improve decision making, and maintain high-quality customer deliverables.
• Applying AI-powered analytics tools to extract insights, identify patterns, and generate actionable recommendations from complex datasets

Position Requirements:

• B.S Electrical/Computer Engineering (or similar degree)
• 4+ years of overall experience
• Experience working with DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 or similar IPs
• Verilog RTL design and gate level verification experience
• Synthesis and static timing analysis experience (physical implementation/verification experience is a plus)
• Familiarity with industry standard DFT flows and test methodologies.
• Familiarity with package and board design
• Ability to read schematics and participate in SI/PI reviews for customer board/package implementation

Preferred Qualifications

• Experience with Memory PHY and DSP based architecture
• Experience with embedded microcontroller FW
• M.S Electrical/Computer Engineering (or similar degree) and 7+ years of overall experience

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