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Cadence System Design and Analysis in Bengaluru is seeking a senior engineer to drive pre-sales engagement and post-sales support for memory subsystem IP, including DDR/LPDDR/HBM/GDDR. You will interface with customers and cross-functional teams to ensure successful deployments of high-performance IP.
The role requires 7+ years in memory IP design/verification, Verilog RTL, timing analysis, DFT, and familiarity with PHY/Controller integration.