Lead Principal Engineer IO Design

Infineon Technologies AG; Bengaluru; On-site; INR 600,000 - 900,000; Full time

Job summary

Infineon Technologies AG in Bengaluru seeks a seasoned IO design leader with 15+ years in analog mixed-signal IO development. You will guide architecture, drive sub-system integration, and ensure quality sign-offs across milestones. You will mentor a small team of designers and review layouts to optimize area, power, and robustness.

The role focuses on LVTTL, LVCMOS, DDR, SPI/xSPI interfaces, and robust verification methodologies, aligning with product requirements and Infineon quality practices.

Qualifications

• 15+ years of solid experience in IO design, preferably for LVTTL/LVCMOS/DDR interfaces.
• Strong understanding of ESD and LU concepts.
• Experience leading small design/layout teams and delivering silicon-ready designs.

Responsibilities

• Lead a team of analog mixed-signal design engineers and own complete IO library development.
• Define IO architecture, specifications, and sub-system integration.
• Ensure IO quality sign-offs and adherence to Infineon processes.

Job description

Your Role

• leading a team of analog mixed signal design engineers, technically and functionally.
• Technically Own complete design & development of IO library designs
• Lead interaction with system architects of product development to close IO specifications & requirements.
• Drive IO integration into the sub-system, resolving all technical issues. Should act as an advisor (Expert support) for the IO selection/Implementations/Integration/qualification at the sub-system.
• Own IO quality sign-off & checklist at different milestones to ensure quality deliverables to SOC.
• Act as an IO architect responsible for defining the overall concept, including the sub-blocks in alignment with product requirements.
• Guide the team members on the effective implementation of the IOs. Review their designs and continuously drive down turnaround time, design robustness/optimisations, and IO area/power.
• Support the FE / BE development hands‑on as per the project needs.
• Continuous improvement and development of design and verification methodologies for improving quality and efficiency.
• Ensuring compliance with all Infineon Quality/Process practices for library development.

Your Profile

• 15+ years of Solid experience in IO design, preferably for interface standards like LVTTL, LVCMOS, DDR, SPI, xSPI, Oscillator, LVDS, overvoltage/under voltage tolerant circuits.
• Good understanding of ESD & LU concepts.
• Good understanding of the characterization methodology used in the IO library development.
• Candidate should be able to technically lead a small team of designers/layout engineers and come up with new architectures and plans/schedules.
• Candidate should have delivered a few designs from spec to silicon with complete knowledge of associated deliverables.
• Disciplined process management, problem‑solving skills, multitasking ability, and attention to quality and detail.
• Demonstrated strong analytical and problem‑solving skills. Strong verbal and written communication skills.
• Ability to work in teams and collaborate effectively with people in different functions.

Contact: Keerthini M H