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NXP Semiconductors in Noida, India, is seeking a Lead DFT Engineer with hands-on experience in scan insertion, ATPG, and GLS to enable robust scan insertion flows during synthesis.
You will model and implement DFT architectures, collaborate across teams, and work with tools like Mentor Tessent, Synopsys DFT Compiler, Cadence Encounter Test, and GLS simulation methods, while following IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG) standards.