Lead DFT design Engineer

Cadence System Design and Analysis; Bengaluru; On-site; INR 2,200,000 - 3,400,000; Full time

Job summary

Cadence System Design and Analysis in Bengaluru is seeking an experienced DFT Engineer with 4–10 years of hands-on experience to lead DFT ownership on multiple ASIC projects.

You will define test architectures, perform scan insertion, ATPG, and timing constraints for test mode timing closure, and ensure adherence to boundary scan and iJTAG/IEEE 1687 standards. Location is Bangalore/Pune.

Qualifications

• 4–10 years of hands-on DFT/IC design experience.
• Experience with scan insertion, LEC checks and low power CLP checks.
• Experience defining timing constraints for test mode timing closure.
• Proficient in ATPG and fault models.
• Knowledge of boundary scan, ACJTAG and IEEE 1500 and iJTAG.
• Experience with IEEE 1687 compliant interfaces.

Responsibilities

• Own DFT architecture and test strategy across projects.
• Identify and implement RTL changes for DFT.
• Perform scan insertion, LEC and CLP checks.
• Develop timing constraints for test mode timing closure.
• Apply scan and ATPG for various fault models.
• Implement boundary scan, ACJTAG, IEEE 1500 and iJTAG for manufacturing tests.
• Coordinate IEEE1687 (iJTAG) compliant ICL/PDL development.

Skills

DFT ownership

RTL changes for DFT

ATPG

Timing constraints for test mode

Boundary scan

IEEE 1687 / iJTAG

IEEE 1500 / ACJTAG

Job description

Experience: 4-10 years

Location - Bangalore/Pune

Responsibilities:

• Complete DFT ownership of projects including: Test architecture definition.
• Identifying and implementing RTL changes for DFT.
• Performing scan insertion, LEC checks, low power CLP checks.
• Developing timing constraints for test mode timing closure.
• Scan and ATPG for different fault models.
• Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
• IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
• Runn...