Lead Design Verification Engineer

Amber Solutions, Inc.; Bengaluru; Remote; INR 4,000,000 - 7,000,000; Full time

Job summary

AmberSemi in Bengaluru seeks a Design Verification Lead Engineer to own the DV strategy for PMIC controllers and SoC subsystems, driving verification closure and signoff.

You will mentor global teams, collaborate with architecture, RTL, firmware, and validation, and lead gate-level, timing-aware, and mixed-signal verification to ensure robust silicon delivery.

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• 10+ years of hands-on ASIC/SoC verification with leadership of at least one complex SoC program.
• Strong SystemVerilog/UVM and C/C++ verification environments experience.

Responsibilities

• Lead DV strategy for PMIC controllers and SoC subsystems.
• Own DV methodology, testbench, coverage, and signoff across IP to full-chip integration.
• Mentor internal and offshore/vendor verification teams and drive verification execution and reviews.
• Collaborate with architecture, RTL design, firmware/software, and system validation teams throughout the product lifecycle.
• Drive verification of ARM and RISC‑V based subsystems.
• Lead gate-level simulation, timing-aware verification, and post-silicon debug activities.
• Execute mixed-signal verification and co-simulation against analog/mixed-signal models.

Skills

SystemVerilog/UVM

C/C++

RTL verification

SoC verification

Debugging

Leadership

Education

Bachelor's or Master's in EE/CE/CS

Tools

Cadence Xcelium

Questa

Synopsys VCS

FPGA-based validation

Job description

We are seeking a talented and motivated Design Verification Lead Engineer with strong technical depth, ownership, and the ability to drive verification closure of digital integrated circuits for a variety of power applications. You will collaborate closely with cross-functional teams to develop innovative solutions that meet customer requirements and industry standards.

The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.

Key Responsibilities

• Lead the definition, planning, development, and execution of comprehensive functional and performance verification strategies for complex PMIC controllers and SoC subsystems.
• Own the end-to-end Design Verification (DV) methodology, including verification planning, UVM testbench architecture, functional and code coverage closure, performance validation, and signoff criteria from IP/block level through full-chip integration.
• Provide technical leadership and mentorship to internal and offshore/vendor verification teams, driving verification execution, reviews, debug activities, and quality deliverables while serving as the primary verification point of contact.
• Collaborate closely with architecture, RTL design, firmware/software, and system validation teams throughout the product lifecycle, from specification definition and architecture reviews to silicon bring-up and post-silicon validation.
• Drive verification of complex processor-based subsystems, including ARM and RISC‑V architectures.
• Lead gate-level simulation, timing‑aware verification and post‑silicon debug activities to ensure robust design signoff and first‑silicon success.
• Execute mixed‑signal verification and co‑simulation methodologies, validating digital control logic against behavioral models of analog and mixed‑signal circuitry, ensuring accurate system‑level functionality and performance.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
• 10+ years of hands‑on ASIC/SoC verification experience, including technical leadership of at least one complex SoC program from verification planning through successful tapeout.
• Demonstrated success in driving functional, code, and assertion coverage closure for complex SoC and IP verification projects, resulting in high‑quality silicon delivery.
• Strong expertise in architecting and developing scalable SystemVerilog/UVM and C/C++-based verification environments from the ground up.
• Proficiency with industry‑standard verification tools and simulators such as Cadence Xcelium, Siemens Questa, and Synopsys VCS, along with experience in FPGA‑based validation platforms.
• Demonstrated leadership skills with the ability to independently plan, prioritize, and execute verification activities while driving alignment and issue resolution across design, architecture, software, and validation teams.
• Strong analytical, debugging, and problem‑solving skills, with a meticulous attention to quality and detail.
• Excellent verbal and written communication skills, with the ability to mentor engineers, influence technical decisions, and effectively collaborate within cross‑functional global teams.

What We Offer

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• A collaborative and innovative work environment.
• The chance to make a significant impact in the semiconductor industry.

Equal opportunities

AmberSemi is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.