Job Posting Title Senior Principal Physical Design Engineer

MaxLinear, Inc.; Bengaluru; On-site; INR 2,000,000 - 3,000,000; Full time

Job summary

MaxLinear, Inc. is seeking a Senior Principal Physical Design Engineer located in Bengaluru, India, with a minimum of 12 years of ASIC physical design experience. The role involves defining execution strategies, leading chip-level PD closure, and collaborating across teams to ensure tapeout readiness.

The ideal candidate should excel in communication and collaboration while managing dynamic environments. A Master's or Bachelor's degree in Electronics/Electrical Engineering is required.

Qualifications

• Minimum 12 years of ASIC physical design experience.
• Excellent collaboration and teamwork capabilities across various chip development disciplines.
• Ability to define and drive flows and methodologies to optimize physical design work.

Responsibilities

• Define execution strategy for large programs.
• Own full-chip PD or major subsystems.
• Drive alignment across ASIC, EDA, layout, and program teams.

Skills

ASIC physical design experience

Collaboration and teamwork

Communication skills

Problem-solving

EDA vendor relationships

Chip architecture understanding

Education

Masters’ / Bachelor’s Degree in Electronics/Electrical Engineering

Job description

Responsibilities

MaxLinear is seeking a Senior Principal Physical Design Engineer with Minimum 12 years of ASIC physical design experience, excellent collaboration and teamwork capabilities, responsible to hire talent and mentor. Ability to define and drive flows and methodologies, resolve design and flow issues, work with front-end teams, and maintain EDA vendor relationships. Multiple successful tape out, strong communication, and ability to handle a dynamic environment.

Define execution strategy for large programs, own full-chip PD or major subsystems, ensure PPA targets and tapeout readiness, drive alignment across teams, new technology adoption, and organization-wide improvements. Ownership of chip-level PD closure, signoff readiness, and delivering silicon for a wide range of applications.

• Define execution strategy for large programs
• Own full-chip PD or major subsystems. Define implementation strategy and ensures PPA targets and tapeout readiness.
• Represent the team in program-level forums. Drive alignment across ASIC, EDA, layout, and program teams.
• Drive new technology adoption, flow definition, and organization-wide improvements.
• Ownership of Chip-level PD closure plan, signoff readiness reviews, escalation playbooks, tool/flow adoption plan, org-wide training artifacts.
• Will be responsible for delivering silicon for a wide range of applications

Qualifications

• Minimum 12 years of ASIC physical design experience
• Should have excellent collaboration and teamwork capabilities across various chip development disciplines. Will be responsible to hire talent and mentor, build expertise, and grow each team member
• Ability to define and drive flows and methodologies to optimize physical design work, define guidelines and checklists, drive execution, and track progress
• Ability to resolve design and flow issues related to physical design through the identification of potential solutions and drive resolution
• Experience in working with the front-end teams to understand chip architecture and drive physical aspects early in the definition cycle
• Experience working relationships with EDA Vendors
• Multiple successful tape out
• Excellent communication (oral and written) skills
• Ability to present to and interface with internal customers
• Ability to handle a dynamic environment and to coordinate team action
• Masters’ / Bachelor’s Degree in Electronics/Electrical Engineering