IP Logic Design Lead

Mulya Technologies; Bengaluru; On-site; INR 2,500,000 - 3,500,000; Full time

Job summary

Mulya Technologies, headquartered in Bangalore, India, seeks an experienced Analog IP RTL Design Engineer to lead a small RTL team and drive world-class IP delivery for customers worldwide.

The role focuses on implementing RTL design from architectural specs, coordinating IP integration, and ensuring quality through lint, CDC, and timing checks. Collaboration with verification and SoC teams is essential.

Qualifications

• Bachelor’s degree in Electrical Engineering (8–10 years RTL development).
• Experience with PCIe/DDR/UCIe IP architecture and industry protocols.
• Strong SystemVerilog, RTL coding, and digital design techniques.
• Proven clock domain crossing (CDC) and timing analysis expertise.
• Hands-on with lint, CDC, RDC, synthesis, timing, regression and code coverage tools.
• Knowledge of AMBA, PCIe, UCIe, and DDR protocols.

Responsibilities

• Lead the small Analog IP RTL design team.
• Implement RTL Design from architectural specs.
• Lead IP RTL integration and sign-off.
• Perform basic quality checks: functionality, lint, CDC, synthesis.
• Define RTL design methodologies, coding standards, simulation flows, and debugging processes.
• Partner with Verification to develop strategies and analyze failures.
• Support SoC integration and resolve IP-level issues.
• Provide technical leadership across verification, PD, and SoC teams.

Skills

SystemVerilog

RTL Coding

Digital Design

CDC

Synthesis

Lint

Timing Analysis

Education

B.E./B.Tech in Electrical Engineering

Tools

Synopsys DC

Cadence Genus

Job description

We are a premium semiconductor design services company headquartered in Bangalore, India. We specialize in the development and delivery of complex Analog and Mixed-Signal IP solutions for leading semiconductor companies worldwide.

Our vision is to become the industry& most trusted partner for turnkey Analog IP development by combining deep technical expertise, execution excellence, and a customer-centric approach. We focus on solving some of the most challenging problems in semiconductor design, from IP migration and process-node portability to performance optimization, feature enhancements, and next-generation IP creation.

We expertise runs across multiple IP types such as:

• High-Speed Serial IPs (SerDes, PCIe, Ethernet)
• Memory and Parallel Interface IPs (DDR, LPDDR, HBM)
• Die-to-Die and Chiplet Connectivity IPs (UCIe)
• Infrastructure and Linear IPs (PLL, DLL, LDO, Voltage Regulators, GPIO, Clocking
• Solutions)

Position Overview

We are seeking a highly motivated Analog Engineers to contribute to the

development and delivery of world-class Analog, Mixed-Signal, and Interface IP

solutions for leading semiconductor customers.

Key Responsibilities

• Lead the small Analog IP RTL design team.
• Implement the RTL Design from (A-specs) architectural specifications.
• Lead and execute IP RTL integration, IP level quality sign-off.
• Perform the basic quality checks such as functionality, lint, CDC, and synthesis checks.
• Define RTL design methodologies, coding standards, simulation flows, and debug
• processes.
• Partner with Design Verification team to develop verification strategies and analyze failures.
• Support SoC integration activities, and resolve IP-level issues.
• Provide technical leadership across verification, physical design, and SoC teams to ensure
• successful IP execution and delivery.

Minimum Qualifications

• Bachelor's degree in Electrical Engineering with 8-10 years of RTL development experience.
• Experience with industry-standard protocols and PCIe/DDR/UCIE IP architecture.
• Strong expertise in SystemVerilog, RTL coding, and advanced digital design techniques.
• Proven experience in clock domain crossing (CDC), microarchitecture/simulation debug, and
• static timing analysis.
• Hands-on experience with LINT, CDC, RDC, synthesis, timing analysis, regression, and code coverage tools.
• Knowledge of AMBA, PCIe, UCIe, and DDR protocols and standards.

Desired Qualifications

• Knowledge of Analog/Digital interface, Analog IP DFX, and Analog block training would be