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Job summary
A leading semiconductor company in Bengaluru is looking for an experienced engineer to lead a small team of 5 to 8 engineers. The role involves designing and verifying complex analog sub-blocks of PCIe, UCIe, and DDR. The ideal candidate should have over 5 years of experience in analog/mixed signal design, strong expertise in transistor level circuit design, and excellent communication skills. The position offers an opportunity to work collaboratively with a team and engage directly with customers.
Qualifications
5 to 8+ years of experience in practical analog/mixed signal design for analog IPs.
Relevant experience with PLL/SERDES, high-speed TX, compensation techniques.
Experience leading a design team is highly preferred.
Responsibilities
Train & lead a small team of 5 to 8 engineers.
Design and verify complex analog sub-blocks of PCIe, UCIe & DDR.
Work with customers to understand sub-block requirements and translate them into design.
Skills
Expert at transistor level circuit design
Expert in noise analysis
Excellent communication skills
Education
B.S. in Electrical Engineering (M.S. preferred)
Tools
EDA tools from Cadence
Simulations from Siemens
Tools from Synopsys
Job description
To train & lead, small team of 5 to 8 engineers.
Design and verification of complex analog sub-blocks of PCIe, UCIe & DDR.
Work with customers to understand sub-block requirement, performance specification & translate that into design.
Work collaboratively with a team of engineers to execute design according to technical specification and schedule in an efficient manner.