HIring for ASIC verification

SmartRecruiters, Inc.; Bengaluru; On-site; INR 1,200,000 - 2,200,000; Full time

Job summary

Happiest Minds is seeking experienced ASIC verification engineers to join our Bangalore-based team. You will develop and maintain robust verification environments using SystemVerilog and UVM/OVM, delivering high-quality testbenches for complex IC designs.

The role requires 5–8 years of hands-on ASIC verification, and proficiency with Synopsys VCS or Mentor Questa. Be part of a fast-moving group delivering cutting-edge solutions in a collaborative environment.

Qualifications

• Proven experience in ASIC verification using SystemVerilog.
• Strong knowledge of UVM/OVM verification methodologies.
• Experience with Industry-standard simulators (VCS/Questa).

Responsibilities

• Implement verification environments using SystemVerilog.
• Apply UVM/OVM methodologies to build scalable testbenches.
• Understand and optimize existing verification flows.
• Contribute to verification methodology development and improvements.

Skills

SystemVerilog

OVM/UVM

Education

BE/B Tech/ME/M Tech - Electronics

Tools

Synopsys VCS

Mentor Questa

Job description

Happiest Minds enables Digital Transformation for enterprises and technology providers by delivering seamless customer experience, business efficiency and actionable insights through an integrated set of disruptive technologies: big data analytics, internet of things, mobility, cloud, security, unified communications, etc. Happiest Minds offers domain centric solutions, IPs in IT Services, Product Engineering, Infrastructure Management and Security. These services have applicability across industry sectors such as retail, CPG, e-commerce, banking, insurance, hi-tech, engineering R&D, manufacturing, automotive and travel/transportation/hospitality. As a Mindful IT Company, the focus is on Being Mindful and Doing Mindful which involves perceiving immersively, processing non-judgmentally and performing empathetically. 60 minutes in a week is committed towards inculcating a mindful approach within the organization, using a select set of tools and techniques. Headquartered in Bangalore, India, Happiest Minds has operations in the US, UK, The Netherlands, Australia, Middle East and Turkey.
For More Information pls go through http://www.happiestminds.com

Job Description

JD for ASIC verification engineers: 5-8 years: 2 positions

• - Implement verification environment independently using high level verification languages like System Verilog

• - OVM/UVM methodology based implementation
• - Experience on Synopsys VCS/ Mentor Questa

• - Understand and execute the existing verification flows and improve the framework
• - Contribute to verification methodology development and implementation

Job Requirements

• - Knowledge of FPGA design and development flow is a plus

Qualifications

BE/B Tech/ME/M Tech - Electronics

By clicking the link above or any third-party link within this posting, you are leaving this site and going to a third-party website where the third-party website's terms and privacy policy apply