ASIC Verification EEJ 2026

SmartRecruiters, Inc.; Bengaluru; On-site; INR 2,000,000 - 3,200,000; Full time

Job summary

Bosch Global Software Technologies Private Limited in Bengaluru seeks a seasoned RTL verification engineer to drive verification of SoCs and automotive ASICs using SystemVerilog and UVM. You will design MDV and/or Formal verification plans, build verification environments from scratch, and track coverage across complex subsystems.

You have 5–10 years of hands-on experience with constrained random verification, AMBA protocols, and tape-out projects, along with Cadence/Synopsys/Mentor tool

Qualifications

• Bachelor's degree in Electronics and Communication.
• 5–10 years in Digital RTL verification.
• Experience with SystemVerilog/UVM in ASIC/SoC work.
• Tape-out participation is a plus.

Responsibilities

• Verify SoCs, automotive ASICs, subsystems and IPs.
• Develop MDV and/or Formal verification plans.
• Create verification environments from scratch.
• Measure regression results and improve flows.
• Collaborate with EDA partners.

Skills

SystemVerilog

UVM

Constrained Random Verification

AMBA Protocols

Scripting (Perl/TCL)

Silicon tapeout experience

Education

BE/B.Tech in Electronics and Communication

Tools

Cadence tools

Synopsys tools

Mentor tools

Job description

• Legal Entity: Bosch Global Software Technologies Private Limited

Company Description

Bosch Global Software Technologies Private Limitedis a 100% owned subsidiary of Robert Bosch GmbH, one of the world's leading global supplier of technology and services, offering end-to-end Engineering, IT and Business Solutions. With over 27,000+ associates, it’s the largest software development center of Bosch, outside Germany, indicating that it is the Technology Powerhouse of Bosch in India with a global footprint and presence in the US, Europe and the Asia Pacific region.

Job Description

Job DescriptionTasks : Verification of SoCs, automotive ASICs, subsystems, IPs.Application of Metric-driven Verification (MDV) and/or Formal Verification methodologiesDeveloping and tracking of Verification plansDevelop verification environments from scratchCreate VIPIntegration of VIP („Verification-IP“ )Measure and analyze regression resultsContinuous improvement of verification methods/tools/flows/processes together with EDA partnersRequirement:5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM.Sound knowledge of constrained random verification, UVM/OVMSound knowledge in SystemVerilog.Experience of developing functional coverage code, coverage analysis.Experience of developing verification environments from scratch is desirable.Good hands on experience with cadence/Synopsys/Mentor tools.Exposure to configuration management, bug tracking tool etc.Knowledge of scripting language, Perl TCL etc.Good experience with AMBA protocolsWorking knowledge on ARM processor-based subsystem/SoC verificationFormal verification experience is a desirable but not must.Must have been a part of one or more ASIC/SoC tape outs.Knowledge of VHDL/VERILOG.SPECMAN knowledge is a desirable but not must

Qualifications

BE / B.Tech / ME / M.Tech (Electronics and Communication)

Additional Information

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