Hardware physical design Engineer

Sunrise Biztech Systems; Karnataka; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Sunrise Biztech Systems seeks an experienced Physical Design Engineer to drive implementation and signoff of high‑performance SoC tiles. The candidate will own end‑to‑end physical design activities from synthesis to tapeout readiness.

You will work on RTL‑to‑GDS flow, focus on timing closure, CTS, PnR, and DRC/LVS, and collaborate with RTL, STA, and PD teams to meet aggressive frequency targets. Strong scripting (Tcl, Python) and experience with high‑frequency designs are a plus, as is ownership

Qualifications

• Experience on high-frequency/high-performance designs.
• ASIC implementation flow from RTL to GDS.
• Ability to independently own and close a design block/tile.

Responsibilities

• Own physical implementation of one or more SoC tiles from synthesis through signoff.
• Perform synthesis and timing optimization to meet aggressive frequency targets.
• Drive Place & Route activities including placement, CTS, routing, and optimization.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup/hold violations.
• Drive DRC, LVS, EMIR, and physical signoff closure.
• Collaborate with RTL, STA, PD methodology, integration, and signoff teams.
• Debug implementation issues and drive schedule execution to tapeout milestones.
• Support ECO implementation and tapeout readiness.

Skills

Logic Synthesis

Static Timing Analysis

Place & Route

Clock Tree Synthesis

Routing & Physical Optimization

Timing Closure

DRC Closure

EMIR Analysis & Fixes

High-Frequency/High-Performance Design

RTL to GDS Flow

Job description

Description: Job Summary

We are seeking an experienced Physical Design Engineer to drive implementation and signoff of high-performance SoC tiles. The candidate will be responsible for end-to-end physical design activities including synthesis, floorplanning support, place and route, timing closure, physical verification, and signoff convergence for high-frequency designs.

Key Responsibilities

• Own physical implementation of one or more SoC tiles from synthesis through signoff.
• Perform synthesis and timing optimization to meet aggressive frequency targets.
• Drive Place & Route activities including placement, CTS, routing, and optimization.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup/hold violations.
• Drive DRC, LVS, EMIR, and physical signoff closure.
• Collaborate with RTL, STA, PD methodology, integration, and signoff teams.
• Debug implementation issues and drive schedule execution to tapeout milestones.
• Support ECO implementation and tapeout readiness.

Required Skills

Strong expertise in:

• Logic Synthesis
• Static Timing Analysis (STA)
• Place & Route (PnR)
• Clock Tree Synthesis (CTS)
• Routing and Physical Optimization
• Timing Closure
• DRC Closure
• EMIR Analysis & Fixes

• Experience working on high-frequency/high-performance designs.
• Strong understanding of ASIC implementation flow from RTL to GDS.
• Ability to independently own and close a design block/tile.

Preferred Qualifications

• Experience on large Server SoCs.
• Experience handling complex timing-critical blocks.
• Strong scripting skills (Tcl, Perl, Python, Shell).
• Experience with industry-standard implementation and signoff tools.
• Strong debugging and problem-solving skills.

Key Selection Criteria

The ideal candidate should demonstrate:

• Proven ownership of complete tile/block implementation.
• Strong timing closure expertise.
• Ability to handle high-frequency designs with minimal supervision.
• Track record of driving block closure under aggressive schedules