Hardware Design Engineer 3- Contract role For Bangalore location

Sunrise Biztech Systems; Hyderabad, Bengaluru; On-site; INR 2,500,000 - 4,200,000; Full time

Job summary

Sunrise Biztech Systems Pvt. Ltd., based in Bangalore, is hiring for a Hardware Design Engineer 3 with 8+ years of hands-on ASIC/RTL verification experience. The role requires a strong background in low-power design challenges and cross-functional collaboration.

You will perform low-power verification across RTL, Synthesis and PnR, execute Formality/LEC checks, and drive signoff closures. The role involves VC-LP tool usage (Synopsys/Cadence) and Conformal ECO processes within a 12-month contract.

Qualifications

• 8+ years of experience in hardware design or ASIC verification.
• Extensive experience with low-power verification techniques and UPF/CPF.
• Experience with RTL to Gate and signoff processes.
• Familiarity with VC-LP, Synopsys or Cadence tools.
• Knowledge of Conformal ECO is a plus.

Responsibilities

• Perform Low-Power Verification using UPF/CPF across RTL, Synthesis, and PnR netlists.
• Execute Formality/LEC Equivalence Checks across RTL-to-RTL, RTL-to-Gate, and Gate-to-PnR.
• Debug low-power and equivalence issues and drive them to signoff closure.
• Collaborate with VC-LP (Synopsys/Cadence) and cross-functional teams.
• Leverage Conformal ECO experience to support digital ASIC flows.

Skills

Low-Power Verification

Equivalence Checks

Debugging

Signoff Closure

Cross-Functional Collaboration

Tools

VC-LP (Synopsys/Cadence)

Conformal ECO

Job description

Urgent Hiring!!!

Greetings from Sunrise Biztech Systems Pvt. Ltd.

We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.

Position: Hardware Design Engineer 3

Experience: 8+ Years

Location: Bangalore

Contract Tenure: 12 months

Key Responsibilities:

• Perform Low-Power Verification using UPF/CPF across RTL, Synthesis, and PnR netlists.
• Execute Formality/LEC Equivalence Checks across RTL-to-RTL, RTL-to-Gate, and Gate-to-PnR.
• Debug low-power and equivalence issues and drive them to signoff closure.
• Work with VC-LP (Synopsys/Cadence) and collaborate with cross-functional teams.
• Experience with FCCheck/VSI closure in digital ASICs; Conformal ECO experience is a plus.